TI DS3885W/883

The DS3885 is one in a series of transceivers designed specifically for the implementation of high performance Futurebus + and proprietary bus interfaces. The DS3885 Arbitration Transceiver is designed to conform to IEEE 1194.1 (Backplane Transceiver Logic BTL). The Arbitration Transceiver incorporates the competition logic internally, which simplifies the implementation of a Futurebus + application by minimizing the on - board logic required. The DS3885 driver output configuration is an NPN open collector, which allows Wired - OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus, thus reducing the bus loading in the inactive state. The BTL drivers also have high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption, and receivers with precision thresholds for maximum noise immunity. BTL eliminates settling time delays that severely limit TTL bus performance and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching. The transceiver’s control and driver inputs are designed with high impedance PNP input structures and are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control, allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI - STATE and fully TTL compatible. The signals ab<7:0> designate the arbitration bus number which this transceiver places on the bus. The signal names AB<7:0> designate the open collector Wired - OR signals on the backplane bus. The DS3885 implements an odd parity check on the arbitration bus bits AB<7:0> with ABP being the parity bit. The signal PER will indicate the parity check result. For a quick indication of current bus conditions, the bus status block generates ALL1 (all asserted) status when all bits (AB<7:0>) are asserted by any module. This signal is used by the DS3875 Arbitration Controller to detect the Arbitration message number (during phase 1) or the powerfail message number (during phase 2). To latch the arbitration number into the transceiver, it is placed onto the CN<7:0> port and the CN LE signal is asserted. When the CMPT signal is asserted, the arbitration number is placed on the bus lines AB<7:0>. The WIN GT signal serves two purposes during the arbitration cycle. If the CMPT signal is not asserted during the arbitration cycle, the transceiver compares its internally latched number to the number on the AB<7:0> bus lines. If the internal number on the transceiver is greater than or equal to the number on the AB<7:0> lines, the WIN GT signal is asserted. However, if the CMPT signal is asserted, the transceiver participates in the competition. If the transceiver wins the arbitration, the WIN GT signal is asserted to confirm the winning. The AB RE signal is used to enable the on - chip receiver outputs. The DS3885 supports live insertion as defined in IEEE 896.2 through the LI (Live Insertion) pin. To implement live insertion, the LI pin should be connected to the live insertion power connector. If this function is not supported, the LI pin must be tied to the VCC pin. The DS3885 also provides glitch free power - up/down protection during power sequencing. The DS3885 has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two VCC pins on the DS3885 that provide the supply voltage for the logic and control circuitry. Multiple power pins reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the VCC bus internal to the device, a voltage difference should never exist between these pins and the voltage difference between VCC and QVCC should never exceed ± 0.5V because of ESD circuitry.

• 9 - bit inverting BTL transceiver
• Meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL)
• Includes on - chip competition logic and parity checking
• Supports live insertion
• Glitch free power - up/down protection
• Typically less than 5 pF bus - port capacitance
• Low bus - port voltage swing (typically 1V) at 80 mA
• Open collector bus - port output allows Wired - OR connection
• Individual bus - port ground pins minimize ground bounce
• Controlled rise and fall time to reduce noise coupling to adjacent lines
• TTL compatible driver and control inputs
• Built in bandgap reference with separate QVCC and QGND pins for precise receiver thresholds
• Product offered in glass sealed CERPAK package style