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TI DS90UB981RTDRQ1 product image
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TI DS90UB981RTDRQ1RoHS

Manufacturer
TI
MPN
DS90UB981RTDRQ1
LCSC Part #
C30123640
Packaging
QFN-64(9x9)
Customer #
Key Attributes
DS90UB981-Q1 4K DSI to FPD-Link IV Bridge Serializer
Datasheetpdf iconTI DS90UB981RTDRQ1
In-Stock: 1,168
1,168 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 15.011$ 15.01
10+$ 14.276$ 142.76
30+$ 13.0038$ 390.11
100+$ 11.8923$ 1189.23
Standard Packaging2000/Full Reel
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Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Serializers, Deserializers
ManufacturerTI
PackagingQFN-64(9x9)
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. When used with an FPD-Link IV deserializer, this chipset provides a high-speed serial interface over low-cost 50Ω coaxial or STP cables. The DS90UB981-Q1 is a D-PHY v1.2-compliant device that serializes MIPI DSI inputs supporting video resolutions up to 4K (30-bit color depth). The FPD-Link IV interface supports video and audio data transmission along with full-duplex control, including I2C and GPIO data transfer over single or dual channels. Consolidating video data and control signals across two FPD-Link IV channels reduces interconnect size and weight while simplifying system design. EMI is minimized through the use of low-voltage differential signaling, data scrambling, spread spectrum clock generation (SSCG), and randomization techniques. In backward-compatible mode, the device supports resolutions up to 720p and 1080p (24-bit color depth) over single/dual links. In ADAS-compatible mode, the device interoperates with 936, 95x, 96x, and 97x deserializers, supporting resolutions up to 8MP+/40fps.

Features

AI Translation
  • Single-port or dual-port MIPI DSI receiver
    • Compliant with D-PHY v1.2 and DSI v1.3.1
    • Supports packed 16/18/24/30-bit RGB and 16-bit YCbCr
    • Supports loosely packed 18-bit RGB and 20-bit 4:2:2
    • 1 clock lane and 1–4 configurable data lanes per D-PHY port
    • Up to 2.5Gbps per lane with skew calibration
    • Supports data lane swap and polarity inversion
    • Supports burst and non-burst modes
    • Super-frame de-packing capability
    • Supports 4K video resolution at 60Hz
  • FPD-Link IV interface
    • Supports 10.8/6.75/3.375Gbps per channel; up to 21.6Gbps dual-channel
    • Supports coaxial cable/STP interconnect
    • Supports port splitting for Y-cable interface
  • Ultra-low latency control channel
    • Two I2C interfaces up to 1MHz (local bus access up to 3.4MHz)
    • High-speed GPIO
  • Backward compatibility
    • 720P 92x and 1080P/2K 94x product families
    • ADAS 936, 954, 960, 962, 9702, 9722 deserializers
  • Safety and diagnostic features
    • Voltage and temperature monitoring
    • Line fault detection
    • Built-in self-test (BIST) and pattern generation
    • CRC and error diagnostics
    • Unique ID for anti-counterfeiting
    • ECC for control bits
  • Advanced link robustness and EMC control
    • Data scrambling
    • Spread spectrum clock generation (SSCG)
  • Low-power operation
    • Dual supply: 1.8V and 1.1V
  • AEC-Q100 qualified for automotive applications
    • AEC-Q100 Grade 2: −40℃ ~ +105℃
    • 64-pin QFN with wettable flanks, 9mm × 9mm
    • Compliant with ISO 10605 and IEC 61000-4-2 ESD standards

Applications

AI Translation
  • Automotive Displays
    • Central Information Display (CID)
    • Rear Seat Entertainment (RSE)
    • Digital Instrument Cluster
    • Head Unit and HMI Module
    • Head-Up Display (HUD)
    • Rear and Side View Mirror Displays