- Pinout Diagram
- Footprint Diagram
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EDA ModelsEasyEDA
STC Micro STC15F2K60S2-28I-LQFP44
| Manufacturer | STC MicroAsian Brands |
| MPN | STC15F2K60S2-28I-LQFP44 |
| LCSC Part # | C29985 |
| Packaging | LQFP-44(10x10) |
| Customer # | |
| Key Attributes | Encrypted microcontroller without the need for an external crystal oscillator and reset |
| Datasheet |  STC Micro STC15F2K60S2-28I-LQFP44 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | LQFP-44(10x10) | |
| ADC (Bit) | 10bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2.4V~3.6V;2.6V~5.5V | |
| Program Memory Type | FLASH | |
| EEPROM | 1KB | |
| Program Storage Size | 60KB | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 28MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 42 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- High-speed: 1 clock/machine cycle, enhanced 8051 core, approximately 12× faster than standard 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 5.5~3.8V, 2.4~3.6V (STC15L101W series)
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- No external reset required; 8 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
- No external crystal required; internal clock configurable from 5MHz~35MHz during ISP programming (equivalent to 8051: 60~420MHz); internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40°C~+85°C), ±0.6% temperature drift at room temperature (-20°C~+65°C)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge), INT2/INT3/INT4 (falling edge); T0/T2 pins; dedicated internal power-down wake-up timer
- 1K/2K/3K/4K/5K/7K bytes on-chip Flash program memory, endurance >100,000 erase/write cycles
- 128-byte on-chip RAM data memory
- On-chip EEPROM, endurance >100,000 erase/write cycles
- ISP/IAP, in-system programmable/in-application programmable, no programmer/emulator required
- 2× 16-bit auto-reload timers T0/T2 with clock output capability; pin MCLKO supports divided internal master clock output (÷1, ÷2, or ÷4)
- Programmable clock output (divides internal system clock or external pin clock input for output): T0 outputs clock on P3.5; T2 outputs clock on P3.0; internal master clock output on P3.4/MCLKO (on STC15 series MCUs with more than 8 pins, master clock outputs on P5.4/MCLKO)
- Hardware watchdog timer (WDT)
- UART functionality implementable via [P3.0/INT4, P3.1] combined with a timer
- Advanced instruction set architecture, compatible with standard 8051 instruction set, with hardware multiply/divide instructions
- 8 general-purpose I/O pins; after reset: quasi-bidirectional/weak pull-up (standard 8051 I/O mode); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin can drive up to 20mA, with a total chip limit of 90mA
- When I/O pins are insufficient, 3 standard I/O lines can interface with a 74HC595 for I/O expansion; multiple chips can be daisy-chained to expand by dozens of I/O pins; ADC-based key scanning can also save I/O pins
- No external crystal required; integrated high-precision R/C clock (±0.3%, ±1% temperature drift (-40°C~+85°C)), ±0.6% temperature drift at room temperature (-20°C~+65°C)
- No external reset required; integrated high-reliability reset circuit; 8 selectable reset threshold voltages during ISP programming; external reset circuit still supported if needed
- Unbreakable encryption — Macroblock 8th-generation encryption technology
- Excellent noise immunity: high ESD protection, passes 20,000V ESD test; passes 4kV EFT test; wide voltage range tolerates power supply fluctuation; wide temperature range: -40°C~+85°C
- Significantly reduced EMI; internally configurable clock; 1 clock/machine cycle; supports low-frequency clock operation
- Ultra-low power consumption: power-down mode wake-up current <0.2μA; idle mode typical current <1mA; normal operating mode: 4mA–6mA; power-down mode wake-up via external interrupt, suitable for battery-powered systems such as water meters, gas meters, and portable devices
- In-system emulation and in-system programming; no dedicated programmer or emulator required; supports remote firmware upgrade
In-Stock: 2,024
2,024 In stock, ships now
Add to BOM List
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.5487 | $ 1.55 |
| 10+ | $ 1.2868 | $ 12.87 |
| 30+ | $ 1.143 | $ 34.29 |
| 160+ | $ 0.9053 | $ 144.85 |
| 480+ | $ 0.8342 | $ 400.42 |
| 960+ | $ 0.8002 | $ 768.19 |
Standard Packaging160/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | STC Micro | |
| Packaging | LQFP-44(10x10) | |
| ADC (Bit) | 10bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2.4V~3.6V;2.6V~5.5V | |
| Program Memory Type | FLASH | |
| EEPROM | 1KB | |
| Program Storage Size | 60KB | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 28MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 42 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- High-speed: 1 clock/machine cycle, enhanced 8051 core, approximately 12× faster than standard 8051, also 20% faster than STC's early 1T series MCUs (e.g., STC12/11/10 series)
- Wide voltage range: 5.5~3.8V, 2.4~3.6V (STC15L101W series)
- Low-power design: slow-speed mode, idle mode, power-down mode (wake-up via external interrupt or internal power-down wake-up timer)
- No external reset required; 8 selectable reset threshold voltages during ISP programming; built-in high-reliability reset circuit
- No external crystal required; internal clock configurable from 5MHz~35MHz during ISP programming (equivalent to 8051: 60~420MHz); internal high-precision R/C clock (±0.3%), ±1% temperature drift (-40°C~+85°C), ±0.6% temperature drift at room temperature (-20°C~+65°C)
- Power-down wake-up sources: INT0/INT1 (rising/falling edge), INT2/INT3/INT4 (falling edge); T0/T2 pins; dedicated internal power-down wake-up timer
- 1K/2K/3K/4K/5K/7K bytes on-chip Flash program memory, endurance >100,000 erase/write cycles
- 128-byte on-chip RAM data memory
- On-chip EEPROM, endurance >100,000 erase/write cycles
- ISP/IAP, in-system programmable/in-application programmable, no programmer/emulator required
- 2× 16-bit auto-reload timers T0/T2 with clock output capability; pin MCLKO supports divided internal master clock output (÷1, ÷2, or ÷4)
- Programmable clock output (divides internal system clock or external pin clock input for output): T0 outputs clock on P3.5; T2 outputs clock on P3.0; internal master clock output on P3.4/MCLKO (on STC15 series MCUs with more than 8 pins, master clock outputs on P5.4/MCLKO)
- Hardware watchdog timer (WDT)
- UART functionality implementable via [P3.0/INT4, P3.1] combined with a timer
- Advanced instruction set architecture, compatible with standard 8051 instruction set, with hardware multiply/divide instructions
- 8 general-purpose I/O pins; after reset: quasi-bidirectional/weak pull-up (standard 8051 I/O mode); four configurable modes: quasi-bidirectional/weak pull-up, strong push-pull/strong pull-up, input-only/high-impedance, open-drain; each I/O pin can drive up to 20mA, with a total chip limit of 90mA
- When I/O pins are insufficient, 3 standard I/O lines can interface with a 74HC595 for I/O expansion; multiple chips can be daisy-chained to expand by dozens of I/O pins; ADC-based key scanning can also save I/O pins
- No external crystal required; integrated high-precision R/C clock (±0.3%, ±1% temperature drift (-40°C~+85°C)), ±0.6% temperature drift at room temperature (-20°C~+65°C)
- No external reset required; integrated high-reliability reset circuit; 8 selectable reset threshold voltages during ISP programming; external reset circuit still supported if needed
- Unbreakable encryption — Macroblock 8th-generation encryption technology
- Excellent noise immunity: high ESD protection, passes 20,000V ESD test; passes 4kV EFT test; wide voltage range tolerates power supply fluctuation; wide temperature range: -40°C~+85°C
- Significantly reduced EMI; internally configurable clock; 1 clock/machine cycle; supports low-frequency clock operation
- Ultra-low power consumption: power-down mode wake-up current <0.2μA; idle mode typical current <1mA; normal operating mode: 4mA–6mA; power-down mode wake-up via external interrupt, suitable for battery-powered systems such as water meters, gas meters, and portable devices
- In-system emulation and in-system programming; no dedicated programmer or emulator required; supports remote firmware upgrade
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |