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SILICON LABS SI5386A-E-GM product image
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SILICON LABS SI5386A-E-GMRoHS

Manufacturer
MPN
SI5386A-E-GM
LCSC Part #
C29954999
Packaging
QFN-64(9x9)
Customer #
Key Attributes
QFN-64(9x9) Clock Generators, PLLs, Frequency Synthesizers RoHS
Datasheetpdf iconSILICON LABS SI5386A-E-GM

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging250
Sales UnitPiece

Introduction

AI Translation

The Si5386 is an ultra high performance wireless jitter attenuator with any frequency outputs for eCPRI (ethernet-based Common Public Radio Interface) applications, which demand the highest level of integration and phase noise performance. The Si5386 combines frequency synthesis and jitter attenuation in a highly integrated digital solution with a cost-effective oscillator, and without the need of any external loop filter components. The fixed frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. The Si5386 architecture is designed to deliver high-performance JESD204B DCLK and SYSREF clock pairs and flexible any-rate clocks for non-CPRI clocks such as Ethernet and system reference clocks all from a single IC.

Features

AI Translation
  • Flexible timing in a single IC
  • Generates any combination of output frequencies from any input frequency
  • Input frequency range:
    • Differential: 7.68 MHz to 750 MHz
    • LVCMOS: 7.68 MHz to 250 MHz
  • Output frequency range (Integer):
    • Differential: up to 2.94912 GHz
  • Output frequency range (fractional):
    • Differential: up to 735 MHz
    • LVCMOS: up to 250 MHz
  • Ultra-low RMS jitter: 72 fs typ (12kHz - 20MHz)
  • Phase noise of 122.88MHz carrier frequency: -118 dBc/Hz @ 100Hz offset
  • ITU-T G.8262 compliant
  • Programmable jitter attenuation bandwidth from 1 Hz to 4 kHz
  • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL. CML outputs can be programmed to have 100 - 1600mVpp single-ended swing.
  • Status monitoring (LOS, OOF, LOL)
  • Pin controlled input switching
  • DSPLL with special wireless calibration
  • Optional zero delay mode
  • Hitless input clock switching: automatic or manual
  • Automatic free-run and holdover modes
  • Fastlock feature
  • Glitchless on the fly output frequency changes
  • Core voltage:
    • VDD: 1.8V ±5%
    • VDDA: 3.3V ±5%
  • Independent output clock supply pins

Applications

AI Translation
  • Wireless Infrastructure
  • eCPRI RRH (Remote Radio Head)
  • BBU (Baseband Unit)
  • Small Cell and μBTS
  • DOCSIS
  • Test and Measurement
In-Stock: 39
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Standard Packaging250/Full Tray
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