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Infineon/CYPRESS CY7C421-25PC product image
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Infineon/CYPRESS CY7C421-25PC

Manufacturer
MPN
CY7C421-25PC
LCSC Part #
C2954789
Packaging
PDIP-28
Customer #
Key Attributes
512x9 25ns 50mA 4.5V~5.5V 28.5MHz PDIP-28 FIFOs Memory
Datasheetpdf iconInfineon/CYPRESS CY7C421-25PC
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.1615$ 0.16
200+$ 0.0625$ 12.50
500+$ 0.0603$ 30.15
1,000+$ 0.0592$ 59.20
Standard Packaging25/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/FIFOs Memory
ManufacturerInfineon/CYPRESS
PackagingPDIP-28
Memory Size512x9
Access Time25ns
Current - Supply(Max)50mA
Voltage - Supply4.5V~5.5V
FeaturesAutomatic retransmission function;Output enable
Clock Frequency28.5MHz
Operating Temperature0℃~+70℃
FunctionAsynchronous
Bus DirectionalUnidirectional
Programmable Flags SupportNo

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging25
Sales UnitPiece

Introduction

AI Translation

CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories available in 600-mil wide and 300-mil wide packages. They have 256, 512, 1024, 2048, and 4096 words respectively, each 9 bits wide. Each FIFO memory is organized so that data is read in the order it was written. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique routes control signals from one device to another in parallel, eliminating the serial accumulation of propagation delays so that throughput is not degraded. Data is routed in a similar manner. Read and write operations can be asynchronous, with each operation at rates up to 50MHz. A write operation occurs when the write signal (W̄) is LOW, and a read operation occurs when the read signal (R̄) is LOW. When R̄ is HIGH, the nine data outputs enter a high-impedance state. A half-full (HF) output flag is provided, which is active in standalone and width-expansion configurations. In a depth-expansion configuration, this pin provides expansion output (XO) information to notify the next FIFO that it has been activated. In standalone and width-expansion configurations, asserting the retransmit (RT) input LOW causes the FIFO to retransmit data. During retransmission, both the read enable (R̄) and write enable (W̄) must be HIGH, after which R̄ is used to access data. CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using advanced 0.65-micron P-well CMOS technology. Input ESD protection exceeds 2000V, and latch-up is prevented through careful layout and guard rings.

Features

AI Translation
  • Asynchronous FIFO buffer memory
    • 256 x 9 (CY7C419)
    • 512 x 9 (CY7C421)
    • 1K x 9 (CY7C425)
    • 2K x 9 (CY7C429)
    • 4K x 9 (CY7C433)
  • Dual-port RAM cell
  • High-speed 50MHz read/write, independent of depth and width
  • Low operating power: ICC = 35mA
  • Empty and full flags (half-full flag in independent mode)
  • TTL compatible
  • Retransmit capability in independent mode
  • Width expandable
  • Available in PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP packages
  • Lead-free packages available
  • Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204