Infineon/CYPRESS PALCE16V8-15JC

Cypress PALCE16V8 is a CMOS flash electrically erasable second-generation programmable array logic device. It employs the common sum-of-products (AND-OR) logic structure with programmable macrocells. The device is available in 20-pin 300-mil molded DIP, 300-mil ceramic DIP, 20-pin square ceramic leadless chip carrier, and 20-pin square plastic leaded chip carrier packages. The device provides up to 16 inputs and 8 outputs, and is electrically erasable and reprogrammable. The programmable macrocells enable the device to function as a superset of common 20-pin PLDs such as the 16L8, 16R8, 16R6, and 16R4. The PALCE16V8 has 8 product terms per output and 32 input terms in the AND array. The first product term in each macrocell can serve as either an internal output enable control or a data product term. The PALCE16V8 macrocell contains 18 architecture bits in total — two are global bits applicable to all macrocells, and 16 are local bits with two per macrocell. The architecture bits determine whether the macrocell operates as registered or combinatorial logic, and whether the output is inverted. Output enable control can be sourced from an external pin or an internal product term. The output can also be permanently enabled as a dedicated output, or permanently disabled as a dedicated input. The feedback path can be selected from the I/O pin associated with the macrocell, the I/O pin associated with an adjacent pin, or the macrocell register itself. All registers in the PALCE16V8 are initialized to logic low at power-up to ensure predictable system initialization. Since the outputs are active low, the output pin corresponding to each register will be at a high level. The PALCE16V8 provides a 64-bit programmable electronic signature word that can contain user-defined data. A security bit is also provided which, when programmed, prevents readback of the internal programming pattern. The Cypress PALCE16V8 achieves low-power operation through CMOS technology and improves testability through flash reprogrammability. Each product term contains a product term disable (PTD) fuse, allowing individual product terms to be disabled independently.

• Data input pins with active pull-ups
• Low-power version (16V8L): commercial (10, 15, 25 ns) max 55 mA; industrial (10, 15, 25 ns) max 65 mA
• Standard version with low power: commercial (10, 15, 25 ns) max 90 mA; commercial (7 ns) max 115 mA; industrial (10, 15, 25 ns) max 130 mA
• CMOS Flash technology — electrically erasable and reprogrammable
• PCI compliant
• User-programmable macrocells: output polarity control; individually selectable registered or combinatorial operation
• Up to 16 inputs and 8 outputs
• Commercial 7.5 ns: tCO 5 ns, tS 5 ns, tPD 7.5 ns, state machine frequency 125 MHz
• Industrial 10 ns: tCO 7 ns, tS 10 ns, tPD 10 ns, state machine frequency 62 MHz
• High reliability: proven Flash technology; 100% programming and functional testing