MICROCHIP PIC18F67J60-I/PT
| Manufacturer | |
| MPN | PIC18F67J60-I/PT |
| LCSC Part # | C29511 |
| Packaging | TQFP-64(10x10) |
| Customer # | |
| Key Attributes | High-Performance, 1-Mbit Flash Microcontrollers with Ethernet |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-64(10x10) | |
| ADC (Bit) | 10bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 41.667MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 39 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- IEEE 802.3(TM) Compatible Ethernet Controller
- Fully Compatible with 10/100/1000Base-T Networks
- Integrated MAC and 10Base-T PHY
- 8-Kbyte Transmit/Receive Packet Buffer SRAM
- Supports One 10Base-T Port
- Programmable Automatic Retransmit on Collision
- Programmable Padding and CRC Generation
- Programmable Automatic Rejection of Erroneous Packets
- Activity Outputs for 2 LED Indicators
- Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for various protocols
- MAC:
- Support for Unicast, Multicast and Broadcast packets
- Programmable Pattern Match of up to 64 bytes within packet at user-defined offset
- Programmable wake-up on multiple packet formats
- PHY:
- Wave shaping output filter
- Selectable System Clock derived from Single 25 MHz External Source: 2.778 to 41.667 MHz
- Internal 31 kHz Oscillator
- Secondary Oscillator using Timer1@32 kHz
- Fail-Safe Clock Monitor: Allows for safe shutdown if oscillator stops
- Two-Speed Oscillator Start-up
- Address Capability of up to 2 Mbytes (100-pin devices only)
- 8-Bit or 16-Bit Interface (100-pin devices only)
- 12-Bit, 16-Bit and 20-Bit Addressing modes (100-pin devices only)
- High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC
- Five Timer modules (Timer0 to Timer4)
- Four External Interrupt pins
- Two Capture/Compare/PWM (CCP) modules
- Three Enhanced Capture/Compare/P
In-Stock: 28
28 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 7.0265 | $ 7.03 |
| 10+ | $ 6.043 | $ 60.43 |
| 30+ | $ 5.4432 | $ 163.30 |
| 100+ | $ 4.9402 | $ 494.02 |
Standard Packaging160/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-64(10x10) | |
| ADC (Bit) | 10bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 41.667MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 39 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 160 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- IEEE 802.3(TM) Compatible Ethernet Controller
- Fully Compatible with 10/100/1000Base-T Networks
- Integrated MAC and 10Base-T PHY
- 8-Kbyte Transmit/Receive Packet Buffer SRAM
- Supports One 10Base-T Port
- Programmable Automatic Retransmit on Collision
- Programmable Padding and CRC Generation
- Programmable Automatic Rejection of Erroneous Packets
- Activity Outputs for 2 LED Indicators
- Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for various protocols
- MAC:
- Support for Unicast, Multicast and Broadcast packets
- Programmable Pattern Match of up to 64 bytes within packet at user-defined offset
- Programmable wake-up on multiple packet formats
- PHY:
- Wave shaping output filter
- Selectable System Clock derived from Single 25 MHz External Source: 2.778 to 41.667 MHz
- Internal 31 kHz Oscillator
- Secondary Oscillator using Timer1@32 kHz
- Fail-Safe Clock Monitor: Allows for safe shutdown if oscillator stops
- Two-Speed Oscillator Start-up
- Address Capability of up to 2 Mbytes (100-pin devices only)
- 8-Bit or 16-Bit Interface (100-pin devices only)
- 12-Bit, 16-Bit and 20-Bit Addressing modes (100-pin devices only)
- High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC
- Five Timer modules (Timer0 to Timer4)
- Four External Interrupt pins
- Two Capture/Compare/PWM (CCP) modules
- Three Enhanced Capture/Compare/P
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |



