Infineon/CYPRESS CY8C9560A-24AXI

The CY8C95xxA is a multi-port I/O expander with on board user available EEPROM and several PWM outputs. All devices in this family operate identically but differ in I/O pins, number of PWMs, and internal EEPROM size.

The CY8C95xxA operates as two I²C slave devices. The first device is a multi port I/O expander (single I²C address to access all ports through registers). The second device is a serial EEPROM. Dedicated configuration registers can be used to disable the EEPROM. The EEPROM uses 2-byte addressing to support the 28 Kbyte EEPROM address space. The selected device is defined by the most significant bits of the I²C address or by specific register addressing.

The I/O expander's data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs. The individual data pins can be configured as open drain or collector, strong drive (10 mA source, 25 mA sink), resistively pulled up or down, or high impedance. The factory default configuration is pulled up internally.

The system master writes to the I/O configuration registers through the I²C bus. Configuration and output register settings are storable as user defaults in a dedicated section of the EEPROM. If user defaults were stored in EEPROM, they are restored to the ports at power up. While this device can share the bus with SMBus devices, it can only communicate with I²C masters. The I²C slave in this device requires that the I²C master supports clock stretching.

There is one dedicated pin that is configured as an interrupt output (INT) and can be connected to the interrupt logic of the system master. This signal can inform the system master that there is incoming data on its ports or that the PWM output state was changed.

The EEPROM is byte readable and supports byte-by-byte writing. A pin can be configured as an EEPROM Write Disable (WD) input that blocks write operations when set high. The configuration registers can also disable EEPROM operations.

The CY8C95xxA has one fixed address pin (A0) and up to six additional pins (A1 - A6), which allow up to 128 devices to share a common two wire I²C data bus. The Extendable Soft Addressing algorithm provides the option to choose the number of pins needed to assign the desired address. Pins not used for address bits are available as GPIO pins.

There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A) independently configurable 8-bit PWMs. These PWMs are listed as PWM0 - PWM15. Each PWM can be clocked by one of six available clock sources.

• I²C interface logic electrically compatible with SMBus
• Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A) I/O data pins independently configurable as inputs, outputs, Bi - directional input/outputs, or PWM outputs
• 4/8/16 PWM sources with 8 - bit resolution
• Extendable soft addressing algorithm allowing flexible I²C address configuration
• Internal 3 - /11 - /27 - Kbyte EEPROM
• User default storage, I/O port settings in internal EEPROM
• Optional EEPROM write disable (WD) input
• Interrupt output indicates input pin level changes and pulse width modulator (PWM) state changes
• Internal power on reset (POR)
• Internal configurable watchdog timer