Infineon/CYPRESS CY96F613RBPMC-GS-130UJE2

CY96610 series is based on Cypress advanced F²M C-16F X architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F²M C-16L X Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.

• 0.18μm CMOS
• F2MC-16FX CPU
• Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)
• 8-byte instruction queue
• Signed multiply (16-bit×16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier [×7] to ×8, ×1 when PLL stop
• 4MHz to 8MHz crystal oscillator (maximum frequency when using ceramic resonator depends on Q-factor)
• Up to 8MHz external clock for devices with fast clock input feature
• 32.768kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog
• Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals
• The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset
• Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)
• Internal voltage regulator supports a wide MCU supply voltage range (Min = 2.7V), offering low power consumption
• Reset is generated when supply voltage falls below programmable reference voltage
• Protects Flash Memory content from unintended read-out
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1Mbps
• 32 message objects
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Extended support for LIN-Protocol to reduce interrupt load
• SAR-type
• 8/10-bit resolution
• Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs
• Range Comparator Function
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
• Hardware watchdog timer is active after reset
• Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
• 16-bit wide
• Prescaler with 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶ of peripheral clock frequency
• Event count function
• Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4)
• Prescaler with 1, 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶, 1/2⁷, 1/2⁸ of peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, Falling edge or Both (rising & falling) edges sensitive
• 16-bit wide
• Signals an interrupt when a match with Free-running Timer occurs
• A pair of compare registers can be used to generate an output signal
• 16-bit down counter, cycle and duty setting registers
• Can be used as 2×8-bit PPG
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as clock input
• Can trigger ADC conversion
• Timing point capture
• Up/down counter