LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Nanya Tech NT5CC256M16DP-DI product image
  • NT5CC256M16DP-DI thumbnail 1
  • NT5CC256M16DP-DI thumbnail 2
  • NT5CC256M16DP-DI thumbnail 3
  • Pinout
  • Footprint
Images for reference only

Nanya Tech NT5CC256M16DP-DIRoHS

Manufacturer
Nanya TechAsian Brands
MPN
NT5CC256M16DP-DI
LCSC Part #
C2943100
Packaging
BGA-96(13x9)
Customer #
Key Attributes
1.35V 4Gbit 800MHz DDR3 SDRAM BGA-96(13x9) Memory (ICs) RoHS
Datasheetpdf iconNanya Tech NT5CC256M16DP-DI
Not available now

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerNanya Tech
PackagingBGA-96(13x9)
Refresh Current-
Voltage - Supply1.35V
Memory Size4Gbit
Operating temperature0℃~+95℃
Clock Frequency800MHz
FeaturesAuto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function
Memory FormatDDR3 SDRAM
Current - Supply-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1000
Sales UnitPiece

Introduction

AI Translation

This 4Gb Double Data Rate 3 (DDR3(L)) DRAM is a high-speed CMOS synchronous DRAM containing 4,294,967,296 bits of storage. It is internally configured as an eight-bank architecture. The 4Gb die is organized as 64M bits × 8 I/O × 8 banks and 32M bits × 16 I/O × 8 banks. These synchronous devices achieve high-speed DDR transfer rates of up to 2133 Mb/s/pin, suitable for general-purpose applications. The die is designed to comply with all key DDR3(L) DRAM features, with all control and address inputs synchronized to a pair of externally supplied differential clocks. Inputs are latched at the crossing point of the differential clock (rising edge of CK and falling edge of CK̄). All I/Os are source-synchronous, referenced to either a single-ended data strobe or a differential data strobe pair. These devices operate from a 1.5V ± 0.075V or 1.35V -0.067V/+0.1V single power supply and are available in BGA packages.

Features

AI Translation
  • Compliant with JEDEC DDR3 standard
  • 8n prefetch architecture
  • Differential clock (CK/CK) and data strobe (DQS/DQS)
  • Double data rate on data I/O, data strobe, and data mask
  • Auto self-refresh via on-die temperature sensor (DRAM)
  • Auto refresh and self-refresh modes
  • Partial array self-refresh
  • Power-down mode
  • Configurable drive strength for improved system compatibility
  • Configurable on-die termination (ODT)
  • ZQ calibration via external ZQ pin (240Ω ± 1%) for drive strength/ODT impedance accuracy
  • Write leveling via mode register settings
  • Read leveling via multipurpose register
  • Interface and power supply: DDR3 SSTL_15, VDD/VDDQ = 1.5V (±0.075V); DDR3L SSTL_135, VDD/VDDQ = 1.35V (-0.067V / +0.1V)
  • Speed grades: 2133 Mbps / 14-14-14, 1866 Mbps / 13-13-13, 1600 Mbps / 11-11-11
  • Temperature range: Commercial = 0°C ~ 95°C, Quasi-Industrial (-T) = -40°C ~ 95°C, Industrial (-I) = -40°C ~ 95°C, Automotive Grade 2 (-H) = -40°C ~ 105°C, Automotive Grade 3 (-A) = -40°C ~ 95°C
  • Programmable features: CAS latency, CAS write latency, additive latency, write recovery time, burst type, burst length, self-refresh temperature range, output driver impedance, ODT nominal value, ODT write value, precharge power-down mode
  • Package/density: Lead-free RoHS compliant and halogen-free