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LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured as an 2-channel memory with 8-bank memory per each channel. These devices contain the following number of bits per die: 4Gb has 4,294,967,296 bits 6Gb has 6,442,450,944 bits 8Gb has 8,589,934,592 bits 12Gb has 12,884,901,888 bits 16Gb has 17,179,869,184 bits 24Gb has 25,769,803,776 bits 32Gb has 34,359,738,368 bits

LPDDR4 devices use multi cycle of single data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 6-bit CA bus contains command, address and bank information. Each command uses two clock cycles, during which command information is transferred on positive edge of the corresponding clock.

These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR4 SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core and sixteen corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.

Prior to normal operation, the LPDDR4 SDRAM must be initialized.

• VDD1 = 1.8V (1.7V to 1.95V)
• VDD2, VDDCA and VDDQ = 1.1V (1.06 to 1.17)
• VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI)
• Single data rate architecture for command and address; - all control and address latched at rising edge of the clock
• Double data rate architecture for data Bus; - two data accesses per clock cycle
• Differential clock inputs (CK_t, CK_c)
• Bi-directional differential data strobe (DQS_t, DQS_c) - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
• DMI pin support for write data masking and DBIdc functionality
• Programmable RL (Read Latency) and WL (Write Latency)
• Burst length: 16 (default), 32 and On-the-fly - On the fly mode is enabled by MRS
• Auto refresh and self refresh supported
• All bank auto refresh and directed per bank auto refresh supported
• Auto TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
• Background ZQ Calibration