micron MT40A1G16RC-062E IT:B

Products Specifications

Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	FBGA-96
Refresh Current	15mA
Memory Size	16Gbit
Voltage - Supply	1.14V~1.26V
Operating temperature	-40℃~+95℃
Clock Frequency	1.6GHz
Features	Auto self-refresh;Auto precharge function;Write leveling function;Data mask function;Dynamic on-chip termination;CRC function;Asynchronous reset function
Memory Format	DDR4 SDRAM
Current - Supply	78mA

AI Translation

VDD = VDDQ = 1.2V ± 60mV
VPP = 2.5V, -125mV, +250mV
On-die, internal, adjustable VREFDQ generation
1.2V pseudo open-drain I/O
TC maximum up to 95℃ – 64ms, 8192-cycle refresh up to 85℃ – 32ms, 8192-cycle refresh at >85℃ to 95℃
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination (ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
JEDEC JESD-79-4 compliant
sPPR and hPPR capability

Not available now

Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	FBGA-96
Refresh Current	15mA
Memory Size	16Gbit
Voltage - Supply	1.14V~1.26V
Operating temperature	-40℃~+95℃
Clock Frequency	1.6GHz
Features	Auto self-refresh;Auto precharge function;Write leveling function;Data mask function;Dynamic on-chip termination;CRC function;Asynchronous reset function
Memory Format	DDR4 SDRAM
Current - Supply	78mA

AI Translation

VDD = VDDQ = 1.2V ± 60mV
VPP = 2.5V, -125mV, +250mV
On-die, internal, adjustable VREFDQ generation
1.2V pseudo open-drain I/O
TC maximum up to 95℃ – 64ms, 8192-cycle refresh up to 85℃ – 32ms, 8192-cycle refresh at >85℃ to 95℃
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination (ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
JEDEC JESD-79-4 compliant
sPPR and hPPR capability