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EDA ModelsEasyEDA
TI OMAPL138EZWTA3
| Manufacturer | |
| MPN | OMAPL138EZWTA3 |
| LCSC Part # | C2879134 |
| Packaging | NFBGA-361 |
| Customer # | |
| Key Attributes | Low-power C674x Floating-point DSP + ARM9 Processor - Up to 456MHz |
| Datasheet |  TI OMAPL138EZWTA3 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microprocessors | |
| Manufacturer | TI | |
| Packaging | NFBGA-361 | |
| CPU Core | Other ARM Series | |
| CPU Maximum Speed | 375MHz |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Dual-Core SoC – 375- and 456-MHz ARM926EJ-S RISC MPU – 375- and 456-MHz C674x Fixed- and FloatingPoint VLIW DSP
- ARM926EJ-S Core – 32- and 16-Bit (Thumb @) Instructions – DSP Instruction Extensions – Single-Cycle MAC – ARM Jazelle Technology – Embedded ICE-RT for Real-Time Debug
- ARM9 Memory Architecture – 16KB of Instruction Cache – 16KB of Data Cache – 8KB of RAM (Vector Table) – 64KB of ROM
- C674x Instruction Set Features – Superset of the C67x+ and Gfx+ ISAs – Up to 3648 MIPS and 2746 MFLOPS – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions
- C674x Two-Level Cache Memory Architecture – 32KB of L1P Program RAM/Cache – 32KB of L1D Data RAM/Cache – 256KB of L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2)
- Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size
- TMS320C674x Floating-Point VLIW DSP Core – Load-Store Architecture With Nonaligned Support – 64 General-Purpose Registers (32-Bit) – Six ALU (32- and 40-Bit) Functional Units – Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point – Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks – Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units: – Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SPxSP→SP Per Clock – 2 SPxSP→DP Every Two Clocks – 2 SPxDP→DP Every Three Clocks – 2 DPxDP→DP Every Four Clocks – Fixed-Point Multiply Supports Two 32x32-Bit Multiplies, Four 16x16-Bit Multiplies, or Eight 8x8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
- Software Support: – TI DSP BIOS – Chip Support Library and DSP Library
- 128KB of RAM Shared Memory
- 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
- Two External Memory Interfaces:
- EMIFA – NOR (8- or 16-Bit-Wide Data) – NAND (8- or 16-Bit-Wide Data) – 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following: – 16-Bit DDR2 SDRAM With 256-MB Address Space – 16-Bit mDDR SDRAM With 256-MB Address Space
- Three Configurable 16550-Type UART Modules: – With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option
- LCD Controller
- Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
- Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
- Two Master and Slave Inter-Integrated Circuits (I²C Bus)
- One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
- Programmable Real-Time Unit Subsystem (PRUSS):
- Two Independent Programmable Real-Time Unit (PRU) Cores
- 32-Bit Load-Store RISC Architecture
- 4KB of Instruction RAM Per Core
- 512 Bytes of Data RAM Per Core
- PRUSS can be Disabled Through Software to Save Power
- Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism
- Clock Gating
- Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
- USB 1.1 OHCI (Host) With Integrated PHY (USB1)
- USB 2.0 OTG Port With Integrated PHY (USB0):
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
- One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
- Two Multichannel Buffered Serial Ports (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
- 10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
- Video Port Interface (VPIF):
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
- Universal Parallel Port (uPP):
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
- Serial ATA (SATA) Controller:
- Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
- Supports All SATA Power-Management Features
- Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
- Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
- One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
- Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Choppin
In-Stock: 71
71 In stock, ships now
Add to BOM List
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 26.4692 | $ 26.47 |
| 3+ | $ 25.7604 | $ 77.28 |
| 30+ | $ 24.48 | $ 734.40 |
Standard Packaging90/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microprocessors | |
| Manufacturer | TI | |
| Packaging | NFBGA-361 | |
| CPU Core | Other ARM Series | |
| CPU Maximum Speed | 375MHz |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Dual-Core SoC – 375- and 456-MHz ARM926EJ-S RISC MPU – 375- and 456-MHz C674x Fixed- and FloatingPoint VLIW DSP
- ARM926EJ-S Core – 32- and 16-Bit (Thumb @) Instructions – DSP Instruction Extensions – Single-Cycle MAC – ARM Jazelle Technology – Embedded ICE-RT for Real-Time Debug
- ARM9 Memory Architecture – 16KB of Instruction Cache – 16KB of Data Cache – 8KB of RAM (Vector Table) – 64KB of ROM
- C674x Instruction Set Features – Superset of the C67x+ and Gfx+ ISAs – Up to 3648 MIPS and 2746 MFLOPS – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions
- C674x Two-Level Cache Memory Architecture – 32KB of L1P Program RAM/Cache – 32KB of L1D Data RAM/Cache – 256KB of L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2)
- Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size
- TMS320C674x Floating-Point VLIW DSP Core – Load-Store Architecture With Nonaligned Support – 64 General-Purpose Registers (32-Bit) – Six ALU (32- and 40-Bit) Functional Units – Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point – Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks – Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units: – Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SPxSP→SP Per Clock – 2 SPxSP→DP Every Two Clocks – 2 SPxDP→DP Every Three Clocks – 2 DPxDP→DP Every Four Clocks – Fixed-Point Multiply Supports Two 32x32-Bit Multiplies, Four 16x16-Bit Multiplies, or Eight 8x8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
- Software Support: – TI DSP BIOS – Chip Support Library and DSP Library
- 128KB of RAM Shared Memory
- 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
- Two External Memory Interfaces:
- EMIFA – NOR (8- or 16-Bit-Wide Data) – NAND (8- or 16-Bit-Wide Data) – 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following: – 16-Bit DDR2 SDRAM With 256-MB Address Space – 16-Bit mDDR SDRAM With 256-MB Address Space
- Three Configurable 16550-Type UART Modules: – With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option
- LCD Controller
- Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
- Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
- Two Master and Slave Inter-Integrated Circuits (I²C Bus)
- One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
- Programmable Real-Time Unit Subsystem (PRUSS):
- Two Independent Programmable Real-Time Unit (PRU) Cores
- 32-Bit Load-Store RISC Architecture
- 4KB of Instruction RAM Per Core
- 512 Bytes of Data RAM Per Core
- PRUSS can be Disabled Through Software to Save Power
- Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism
- Clock Gating
- Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
- USB 1.1 OHCI (Host) With Integrated PHY (USB1)
- USB 2.0 OTG Port With Integrated PHY (USB0):
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
- One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
- Two Multichannel Buffered Serial Ports (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
- 10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
- Video Port Interface (VPIF):
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
- Universal Parallel Port (uPP):
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
- Serial ATA (SATA) Controller:
- Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)
- Supports All SATA Power-Management Features
- Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
- Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
- One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
- Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Choppin
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |