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TI TPIC6B596DWRRoHS

Manufacturer
MPN
TPIC6B596DWR
LCSC Part #
C2878451
Packaging
SOIC-20-300mil
Customer #
Key Attributes
8-Bit Shift Register
Datasheetpdf iconTI TPIC6B596DWR
In-Stock: 190
190 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.4474$ 1.45
10+$ 1.2836$ 12.84
30+$ 1.1683$ 35.05
100+$ 1.0629$ 106.29
500+$ 1.0142$ 507.10
1,000+$ 0.9947$ 994.70
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Shift Registers
ManufacturerTI
PackagingSOIC-20-300mil
Operating temperature-40℃~+125℃
Voltage - Supply4.5V~5.5V
Output TypeOpen-drain
Output Current150mA
FeaturesAsynchronous clear function;Output enable
Propagation Delay15ns@5V,30pF
FunctionSerial-to-Parallel

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOStransistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150 mA continuous sinkcurrent capability. Each output provides a 500 mA typical current imit at Tc = 25℃. The current limit decreases as the junction temperature increases for additional device protection. racterized for operation over the operating case temperature range of -40℃ to 125℃

Features

AI Translation
  • Low rDS(on) ... 5 Ω
  • Avalanche Energy ... 30 mJ
  • Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current
  • 500-mA Typical Current-Limiting Capability
  • Output Clamp Voltage ... 50 V
  • Enhanced Cascading for Multiple Stages
  • All Registers Cleared With Single Input
  • Low Power Consumption