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TI CD4019BM96
| Manufacturer | |
| MPN | CD4019BM96 |
| LCSC Part # | C2878073 |
| Packaging | SOIC-16 |
| Customer # | |
| Key Attributes | CMOS Quad AND/OR Select Gate |
| Datasheet |  TI CD4019BM96 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Input Logic Level - High | 3.5V;7V;11V | |
| Input Logic Level - Low | 1.5V;3V;4V | |
| Logic Family | 4000B Series | |
| Propagation Delay | 100ns@15V | |
| Current - Output Low(IOL) | 4.2mA | |
| Output Logic Level - High | 4.95V;9.95V;14.95V | |
| Quiescent Current(Iq) | 30uA | |
| Current - Output High(IOH) | 4.2mA | |
| Voltage - Supply | 3V~18V | |
| Features | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Channels | 4 | |
| Output Logic Level - Low | 50mV |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
Features
AI Translation
- Medium-speed operation: tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25℃
- Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
Applications
AI Translation
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection
In-Stock: 1,004
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.4164 | $ 0.42 |
| 10+ | $ 0.327 | $ 3.27 |
| 30+ | $ 0.2831 | $ 8.49 |
| 100+ | $ 0.244 | $ 24.40 |
| 500+ | $ 0.2343 | $ 117.15 |
| 1,000+ | $ 0.2278 | $ 227.80 |
Standard Packaging2500/Full Reel | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Input Logic Level - High | 3.5V;7V;11V | |
| Input Logic Level - Low | 1.5V;3V;4V | |
| Logic Family | 4000B Series | |
| Propagation Delay | 100ns@15V | |
| Current - Output Low(IOL) | 4.2mA | |
| Output Logic Level - High | 4.95V;9.95V;14.95V | |
| Quiescent Current(Iq) | 30uA | |
| Current - Output High(IOH) | 4.2mA | |
| Voltage - Supply | 3V~18V | |
| Features | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Channels | 4 | |
| Output Logic Level - Low | 50mV |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
Features
AI Translation
- Medium-speed operation: tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25℃
- Noise margin (full package-temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
Applications
AI Translation
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |