LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
TI DS90LV032ATM/NOPB product image
Images for reference only

TI DS90LV032ATM/NOPBRoHS

Manufacturer
MPN
DS90LV032ATM/NOPB
LCSC Part #
C2878018
Packaging
SOIC-16
Customer #
Key Attributes
3-V LVDS Quad CMOS Differential Line Receiver
Datasheetpdf iconTI DS90LV032ATM/NOPB
In-Stock: 41
41 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 3.323$ 3.32
10+$ 2.879$ 28.79
48+$ 2.6155$ 125.54
96+$ 2.3487$ 225.48
480+$ 2.2268$ 1068.86
1,008+$ 2.1715$ 2188.87
Standard Packaging48/Full Tube
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers
ManufacturerTI
PackagingSOIC-16
Voltage - Supply3V~3.6V
TypeReceiver
Data Rate400Mbps
Operating Temperature-40℃~+85℃
Number of Drivers0
FeaturesFail-safe
Level StandardLVDS
Number of Receivers4

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging48
Sales UnitPiece

Introduction

AI Translation

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV032A accepts low voltage (350 mv typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100 Ω) input Fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV032A and companion LVDS line driver (for example, DS90LV031A) provide a new alternative to high power PECL or ECL devices for high speed point-to-point interface applications.

Features

AI Translation
  • 400 Mbps (200 MHz) Switching Rates

  • 0.1-ns Channel-to-Channel Skew (Typical)
  • 0.1-ns Differential Skew (Typical)
  • 3.3-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • Power Down High Impedance on LVDS Inputs
  • Low Power Design (40 mW at 3.3 V Static)
  • Interoperable With Existing 5-V LVDS Networks
  • Accepts Small Swing (350 mV Typical) VID
  • Supports Open, Short, and Terminated Input Fail Safe
  • Compatible With ANSI/TIA/EIA-644
  • Industrial Temperature Operating Range (-40°C to 85°C)
  • Available in SOIC and TSSOP Packaging

Applications

AI Translation
  • Building And Factory Automation Grid Infrastructure