LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
TI SN74LVC1G80DBVT product image
  • SN74LVC1G80DBVT thumbnail 1
  • SN74LVC1G80DBVT thumbnail 2
  • SN74LVC1G80DBVT thumbnail 3
  • Pinout Diagram
  • Footprint Diagram
Images for reference only

TI SN74LVC1G80DBVTRoHS

Manufacturer
MPN
SN74LVC1G80DBVT
LCSC Part #
C2877798
Packaging
SOT-23-5
Customer #
Key Attributes
SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop
Datasheetpdf iconTI SN74LVC1G80DBVT
In-Stock: 146
146 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.4411$ 0.44
10+$ 0.3532$ 3.53
30+$ 0.3158$ 9.47
250+$ 0.2702$ 67.55
500+$ 0.2491$ 124.55
1,000+$ 0.236$ 236.00
Standard Packaging250/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingSOT-23-5
Operating Temperature-40℃~+125℃
Voltage - Supply1.65V~5.5V
Number of Bits per Element1
Series74LVC Series
Output Type-
Number of Elements1
Current - Output High(IOH)32mA
Current - Output Low(IOL)32mA
Setup Time1.1ns
Quiescent Current10uA
Hold Time400ps
Propagation Delay4.5ns@5V,50pF
Trigger TypeRising Edge

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging250
Sales UnitPiece

Introduction

AI Translation

The SN74LVC1G80 device is a single positive-edge-triggered D-type flip-flop designed for 1.65V to 5.5V VCC operation. When the data at the data (D) input meets the setup time requirements, that data is transferred to the Q output on the positive edge of the clock pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, the data at the D input can be changed without affecting the output level. NanoFree package technology represents a major breakthrough in IC packaging concepts, using the die itself as the package. The device is fully suitable for partial power-down applications using Ioff. When the device is powered down, the Ioff circuit disables the outputs. This suppresses backflow current into the device, thereby preventing device damage.

Features

AI Translation
  • NanoFree package
  • Latch-up performance exceeds 100mA, compliant with JESD 78 Class II specification
  • ESD protection performance exceeds JESD 22 specification requirements: 2000V Human Body Model (A114-A), 200V Machine Model (A115-A), 1000V Component Charged Device Model (C101)
  • Supports 5V VCC operation, inputs accept voltages up to 5.5V
  • Supports down-translation to VCC 3.3V with maximum tpd of 4.2ns
  • Low power consumption, 10μA maximum ICC
  • Output drive ±24mA at 3.3V
  • Supports partial power-down mode and back-drive protection

Applications

AI Translation
  • Test and Measurement
  • Enterprise Switching
  • Telecom Infrastructure
  • Consumer Electronics
  • White Goods