TI SN65DSI84ZXHR

Implement the physical layer front - end of MIPI D - PHY version 1.00.00 and the single - channel DSI receiver of the Display Serial Interface (DSI) version 1.02.00. Each channel can be configured for 1, 2, 3, or 4 D - PHY data channels. The operating rate of each channel is up to 1 Gbps. It supports 18bpp and 24bpp DSI video packets in RGB666 and RGB888 formats, suitable for 60fps WUXGA 1920 × 1200 resolution (18bpp and 24bpp color) and 60fps 1366 × 768 (18bpp and 24bpp). Flatlink supports output configuration for single - link or dual - link LVDS and the operating mode from single - channel DSI to dual - link LVDS. In dual - link or single - link mode, the LVDS output clock range is from 25 MHz to 154 MHz. The LVDS pixel clock can use a free - running continuous D - PHY clock or an external reference clock (REFCLK). It has a 1.8V main VCC power supply. Low - power features include shutdown mode, low LVDS output voltage swing, common mode, and MIPI Ultra - Low Power State (ULPS). It supports LVDS channel swapping (SWAP) for simplified printed circuit board (PCB) routing and the LVDS pin - order reversal feature. The electrostatic discharge (ESD) rating is ±2 kV (Human Body Model (HBM)). It is packaged in a 64 - pin 5mm×5mm BGA (ZQE) package. The temperature range is from - 40°C to 85°C.

The SN65DSI84 DSI to FlatLink bridge uses a single - channel MIP D - PHY receiver front - end configuration, which has 4 channels on each channel, and the operating rate of each channel is 1 Gbps; the maximum input bandwidth is 4 Gbps. This bridge decodes MIP DSI 18bpp RGB666 and 24bpp RGB888 packets and converts the formatted video data stream into a FlatLink - compatible LVDS output running on a pixel clock with a frequency range between 25 MHz and 154 MHz, thereby providing a single - link LVDS with 4 data channels per link. The SN65DSI84 is very suitable for 60fps WUXGA 1920 x1200 applications with up to 24 bits per pixel. The device implements partial line buffering to adapt to the data - flow mismatch between the DSI and LVDS interfaces. The SN65DSI84 is designed with industry - standard interface technology, can be compatible with a variety of microprocessors, and has a variety of power - management features, including low - swing LVDS output and support for the MIPI - defined Ultra - Low Power State (ULPS). The SN65DSI84 is packaged in a small - form - factor 5x5mm BGA package (with a ball pitch of 0.5mm) and operates in a temperature range from - 40°C to 85°C.

• Implements MIPI D-PHY version 1.00.00 physical layer front-end and version 1.02.00 Display Serial Interface (DSI)
• Single-port DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per port, operating at up to 1Gbps per lane
• Supports 18bpp and 24bpp DSI video packets in RGB666 and RGB888 formats
• Supports 60fps WUXGA 1920 × 1200 resolution (18bpp and 24bpp color) and 60fps 1366 × 768 (18bpp and 24bpp)
• Flatlink output configuration for single-link or dual-link LVDS
• Supports single-port DSI to dual-link LVDS operation mode
• LVDS output clock range 25MHz to 154MHz in dual-link or single-link mode
• LVDS pixel clock accepts free-running continuous D-PHY clock or external reference clock (REFCLK)
• 1.8V main VCC supply
• Low-power features include shutdown mode, low LVDS output voltage swing, common mode, and MIPI Ultra-Low Power State (ULPS) support
• LVDS lane swap and LVDS pin polarity inversion for simplified PCB routing
• ESD rating ±2kV (HBM)
• 64-pin 5mm × 5mm BGA (ZQE) package
• Temperature range: -40°C to 85°C

• Tablet PCs
• Laptops
• Netbook mobile internet devices