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TI CD74HCT597M96
| Manufacturer | |
| MPN | CD74HCT597M96 |
| LCSC Part # | C2873076 |
| Packaging | SOIC-16 |
| Customer # | |
| Key Attributes | 4.5V~5.5V 1 50mA 16ns@5V,15pF Parallel-to-Serial SOIC-16 Shift Registers RoHS |
| Datasheet |  TI CD74HCT597M96 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Operating temperature | -55℃~+125℃ | |
| Pd - Power Dissipation | - | |
| Voltage - Supply | 4.5V~5.5V | |
| Output Type | - | |
| Series | 74HCT | |
| Number of Elements | 1 | |
| Output Current | 50mA | |
| Features | Asynchronous clear function;Asynchronous parallel load function | |
| Propagation Delay | 16ns@5V,15pF | |
| Function | Parallel-to-Serial |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A “low” on the parallel load input (PL (overline)) shifts parallel stored data asynchronously into the shift register. A “low” master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL (overline) is high.
Features
- Buffered Inputs
- Asynchronous Parallel Load
- Fanout (Over Temperature Range) - Standard Outputs: 10 LSTTL Loads; Bus Driver Outputs: 15 LSTTL Loads
- Wide Operating Temperature Range: -55℃ to 125℃
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types:
- 2V to 6V Operation
- High Noise Immunity: N parallel L = 30%, N 1H = 30% of V cc at V cc = 5V
- HCT Types:
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V parallel L = 0.8V (Max), ∇ parallel H = 2V (Min)
- CMOS Input Compatibility, I parallel ≤ 1μA at all V 0L, V 0H
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.4427 | $ 0.44 |
| 10+ | $ 0.3487 | $ 3.49 |
| 30+ | $ 0.3016 | $ 9.05 |
| 100+ | $ 0.2595 | $ 25.95 |
| 500+ | $ 0.2481 | $ 124.05 |
| 1,000+ | $ 0.2417 | $ 241.70 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Shift Registers | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Operating temperature | -55℃~+125℃ | |
| Pd - Power Dissipation | - | |
| Voltage - Supply | 4.5V~5.5V | |
| Output Type | - | |
| Series | 74HCT | |
| Number of Elements | 1 | |
| Output Current | 50mA | |
| Features | Asynchronous clear function;Asynchronous parallel load function | |
| Propagation Delay | 16ns@5V,15pF | |
| Function | Parallel-to-Serial |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A “low” on the parallel load input (PL (overline)) shifts parallel stored data asynchronously into the shift register. A “low” master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL (overline) is high.
Features
- Buffered Inputs
- Asynchronous Parallel Load
- Fanout (Over Temperature Range) - Standard Outputs: 10 LSTTL Loads; Bus Driver Outputs: 15 LSTTL Loads
- Wide Operating Temperature Range: -55℃ to 125℃
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types:
- 2V to 6V Operation
- High Noise Immunity: N parallel L = 30%, N 1H = 30% of V cc at V cc = 5V
- HCT Types:
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V parallel L = 0.8V (Max), ∇ parallel H = 2V (Min)
- CMOS Input Compatibility, I parallel ≤ 1μA at all V 0L, V 0H
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |