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TI SN74ABT16373ADGGRRoHS

Manufacturer
TI
MPN
SN74ABT16373ADGGR
LCSC Part #
C2872686
Packaging
TSSOP-48-6.1mm
Customer #
Key Attributes
16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Datasheetpdf iconTI SN74ABT16373ADGGR
In-Stock: 57
57 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.9379$ 1.94
10+$ 1.7056$ 17.06
30+$ 1.5435$ 46.31
100+$ 1.3938$ 139.38
500+$ 1.3252$ 662.60
1,000+$ 1.2972$ 1297.20
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Latches
ManufacturerTI
PackagingTSSOP-48-6.1mm
Quiescent Current2mA
Series74ABT
Logic TypeD Latch
Voltage - Supply4.5V~5.5V
Operating Temperature-40℃~+85℃
Current - Output Low(IOL)64mA
Output TypeTri-State
Current - Output High(IOH)32mA
Number of Channels16
Setup Time1.5ns
Hold Time1ns
Propagation Delay4ns
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

The ’ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE(overline)) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16373A is characterized for operation from -40℃ to 85℃.

Features

AI Translation
  • State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical vOLP (Output Ground Bounce) <0.8 V at Vcc = 5 V, TA = 25℃
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Applications

AI Translation
  • Buffer register
  • I/O port
  • Bidirectional bus driver
  • Working register