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TI SN74LVC1G74DQERRoHS

Manufacturer
TI
MPN
SN74LVC1G74DQER
LCSC Part #
C2870716
Packaging
X2-SON-8(1x1.4)
Customer #
Key Attributes
Single-channel rising-edge triggered D-type flip-flop with clear and preset functions
Datasheetpdf iconTI SN74LVC1G74DQER
In-Stock: 200
200 In stock, ships now
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QtyUnit PriceTotal Amount
5+$ 0.3565$ 1.78
50+$ 0.282$ 14.10
150+$ 0.25$ 37.50
500+$ 0.2102$ 105.10
2,500+$ 0.1925$ 481.25
5,000+$ 0.1818$ 909.00
Standard Packaging5000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingX2-SON-8(1x1.4)
Operating Temperature-40℃~+125℃
Voltage - Supply1.65V~5.5V
Number of Bits per Element1
Synchronous/AsynchronousAsynchronous
Current - Output High(IOH)16mA
Number of Elements1
Current - Output Low(IOL)16mA
Quiescent Current10uA
Setup Time1.1ns
Hold Time500ps
Propagation Delay2.6ns@3.3V,30pF
Trigger TypeRising Edge
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Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging5000
Sales UnitPiece

Introduction

AI Translation

This single-bit, positive-edge-triggered D-type flip-flop operates from 1.65V to 5.5V VCC. NanoFree™ packaging technology represents a significant breakthrough in IC packaging concepts, using the silicon die itself as the package. A low level on the preset (PRE) or clear (CLR) input sets or resets the output regardless of the levels of other inputs. When PRE and CLR are inactive (high), data at the D input that meets the setup time requirement is transferred to the output on the positive edge of the clock pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, the data at the D input can be changed without affecting the output level. This device fully meets the specifications for partial power-down applications using Ioff. The Ioff circuit disables the outputs, preventing destructive backflow current from the device when it is powered down.

Features

AI Translation
  • NanoFree™ package
  • 5V VCC operation
  • Inputs accept up to 5.5V
  • Down translation to VCC
  • tpd max 5.9ns at 3.3V
  • Low power, ICC max 10μA
  • ±24mA output drive at 3.3V
  • VOLP (output ground bounce) typ < 0.8V (VCC = 3.3V, TA = 25℃)
  • VOHV (output VOH undershoot) typ > 2V (VCC = 3.3V, TA = 25℃)
  • Ioff supports hot insertion, partial power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78 Class II
  • ESD protection exceeds JESD 22
    • 2000V Human Body Model
    • 200V Machine Model
    • 1000V Charged Device Model

Applications

AI Translation
  • Servers
  • LED displays
  • Network switches
  • Telecom infrastructure
  • Motor drivers
  • I/O expanders