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TI SN74LV11ADRRoHS

Manufacturer
TI
MPN
SN74LV11ADR
LCSC Part #
C2870702
Packaging
SOIC-14
Customer #
Key Attributes
TRIPLE 3-INPUT POSITIVE-AND GATES
Datasheetpdf iconTI SN74LV11ADR
In-Stock: 210
210 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.6338$ 0.63
10+$ 0.5415$ 5.42
30+$ 0.4766$ 14.30
100+$ 0.4215$ 42.15
500+$ 0.4053$ 202.65
1,000+$ 0.3956$ 395.60
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerTI
PackagingSOIC-14
FeaturesLocal shutdown mode
Input Logic Level - Low500mV
Logic Family74LV Series
Operating Temperature-40℃~+85℃
Input Logic Level - High1.5V
Output Logic Level - High2V;2.48V;3.8V
Quiescent Current(Iq)20uA
Voltage - Supply2V~5.5V
Current - Output High(IOH)12mA
Number of Channels3;3
Output Logic Level - Low100mV;400mV;440mV;550mV
Propagation Delay7.9ns@5V,50pF
Current - Output Low(IOL)12mA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation. The ’LV11A devices perform the Boolean function Y = A • B • C or Y = A(overline) + B(overline) + C(overline)(overline) in positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Features

AI Translation
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5V
  • Typical vOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
  • Typical vOHV (Output v0H Undershoot) > 2.3V at VCC = 3.3V, TA = 25℃
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)