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TI SN74AHC123APWRRoHS

Manufacturer
MPN
SN74AHC123APWR
LCSC Part #
C2869599
Packaging
TSSOP-16
Customer #
Key Attributes
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
Datasheetpdf iconTI SN74AHC123APWR

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Multivibrators
ManufacturerTI
PackagingTSSOP-16
Input TypeSchmitt trigger
Logic TypeMonostable
Number Of Channels2

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

The 'AHC123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V Vcc operation. These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A(overline) input is low, and the B input goes high. In the second method, the B input is high, and the A(overline) input goes low. In the third method, the A(overline) input is low, the B input is high, and the clear (CLR(overline)) input goes high. The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A(overline), B, and CLR(overline) inputs have Schmit trigers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A(overline)) Or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to overide A(overline) or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. During power up, Q outputs are in the low state, and Q(overline) outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

Features

AI Translation
  • Operating Range 2-V to 5.5-V Vcc
  • Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset On Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD78, Class II
  • ESD Protection Exceeds JESD22 - 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
In-Stock: 2,237
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Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.5076$ 0.51
10+$ 0.4103$ 4.10
30+$ 0.3616$ 10.85
100+$ 0.3195$ 31.95
500+$ 0.3081$ 154.05
1,000+$ 0.3017$ 301.70
Standard Packaging2000/Full Reel
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