LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
TI SN74ALVCH245PWR product image
  • SN74ALVCH245PWR thumbnail 1
  • SN74ALVCH245PWR thumbnail 2
  • SN74ALVCH245PWR thumbnail 3
  • Pinout
  • Footprint
Images for reference only

TI SN74ALVCH245PWRRoHS

Manufacturer
MPN
SN74ALVCH245PWR
LCSC Part #
C2867080
Packaging
TSSOP-20
Customer #
Key Attributes
Octal Bus Transceiver with 3-State Outputs
Datasheetpdf iconTI SN74ALVCH245PWR
In-Stock: 45
45 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.4516$ 0.45
10+$ 0.442$ 4.42
30+$ 0.4356$ 13.07
100+$ 0.4292$ 42.92
Standard Packaging2000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerTI
PackagingTSSOP-20
Current - Output High(IOH)24mA
Voltage - Supply1.65V~3.6V
Series74ALVCH
Operating Temperature-40℃~+85℃
Output TypeTri-State
Current - Output Low(IOL)24mA
Number of Bits per Element8
Channel TypeBidirectional
FeaturesBus hold;Output enable
Number of Elements1
Propagation Delay3.4ns@3.3V,50pF
Quiescent Current10uA

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE(overline)) input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Features

AI Translation
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.4 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II