High- Performance Digital Media Processor 2- , 1.67- , 1.39- ns Instruction Cycle Time 500- , 600- , 720- MHz Clock Rate Eight 32- Bit Instructions/Cycle 4000, 4800, 5760 MIPS Fully Software- Compatible With C64xTM VelociTI.2TM Extensions to VelociTI TM Advanced Very- Long- Instruction- Word (VLIW) TMS320C64xTM DSP Core Eight Highly Independent Functional Units With VelociTI.2TM Extensions: Six ALUs (32- /40- Bit), Each Supports Single 32- Bit, Dual 16- Bit, or Quad 8- Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16- Bit Multiplies (32- Bit Results) per Clock Cycle or Eight 8 x 8- Bit Multiplies (16- Bit Results) per Clock Cycle Load- Store Architecture With Non- Aligned Support 64 32- Bit General- Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Byte- Addressable (8- /16- /32- /64- Bit Data) 8- Bit Overflow Protection Bit- Field Extract, Set, Clear Normalization, Saturation, Bit- Counting VelociTI.2TM Increased Orthogonality L1/L2 Memory Architecture 128K- Bit (16K- Byte) L1P Program Cache (Direct Mapped) 128K- Bit (16K- Byte) L1D Data Cache (2- Way Set- Associative) 2M- Bit (256K- Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 64- Bit External Memory Interface (EMIF) Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
TI TMS320DM642AGDKA6