TI SN74ABT16543DGGR
| Manufacturer | |
| MPN | SN74ABT16543DGGR |
| LCSC Part # | C2865087 |
| Packaging | TSSOP-56 |
| Customer # | |
| Key Attributes | 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| Datasheet |  TI SN74ABT16543DGGR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | TSSOP-56 | |
| Input type | - | |
| Current - Output High(IOH) | 32mA | |
| Series | 74ABT | |
| Voltage - Supply | 4.5V~5.5V | |
| Operating Temperature | -40℃~+85℃ | |
| Output Type | Tri-State | |
| Current - Output Low(IOL) | 64mA | |
| Number of Bits per Element | 8 | |
| Channel Type | Bidirectional | |
| Features | Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 2.5ns@5V,50pF | |
| Quiescent Current | 2mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 'ABT16543' 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Features
- State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLO (Output Ground Bounce) < 1V at VCC = 5V, TA = 25℃
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IoH, 64-mA IoL)
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 2.4304 | $ 2.43 |
| 10+ | $ 2.0442 | $ 20.44 |
| 30+ | $ 1.8011 | $ 54.03 |
| 100+ | $ 1.5516 | $ 155.16 |
| 500+ | $ 1.439 | $ 719.50 |
| 1,000+ | $ 1.3907 | $ 1390.70 |
Standard Packaging2000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | TSSOP-56 | |
| Input type | - | |
| Current - Output High(IOH) | 32mA | |
| Series | 74ABT | |
| Voltage - Supply | 4.5V~5.5V | |
| Operating Temperature | -40℃~+85℃ | |
| Output Type | Tri-State | |
| Current - Output Low(IOL) | 64mA | |
| Number of Bits per Element | 8 | |
| Channel Type | Bidirectional | |
| Features | Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 2.5ns@5V,50pF | |
| Quiescent Current | 2mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 'ABT16543' 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Features
- State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLO (Output Ground Bounce) < 1V at VCC = 5V, TA = 25℃
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IoH, 64-mA IoL)
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |