TI SN74LVC2G74DCURG4

This single-bit positive edge-triggered D-type flip-flop operates at VCC ranging from 1.65V to 5.5V. NanoFree™ package technology represents a major breakthrough in IC packaging concepts, using the silicon die itself as the package. A low level on the preset (PRE) or clear (CLR) input sets or resets the output regardless of the levels of other inputs. When PRE and CLR are inactive (high), data at the D input that meets the setup time requirement is transferred to the output on the positive edge of the clock pulse. Clock triggering occurs at a specified voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, the data at the D input can be changed without affecting the output level. This device fully complies with the specifications for partial power-down applications using Ioff. The Ioff circuit disables the outputs, preventing damaging current backflow through the device when it is powered down.

• NanoFree™ package
• 5V VCC operation
• Input voltage up to 5.5V
• tpd max 5.9ns at 3.3V
• Low power consumption, ICC max 10μA
• ±24mA output drive at 3.3V
• VOLP (output ground bounce) typical <0.8V (VCC = 3.3V, TA = 25℃)
• VOHV (output VOH undershoot) typical >2V (VCC = 3.3V, TA = 25℃)
• Ioff supports hot insertion, partial power-down mode, and back-drive protection
• Latch-up performance exceeds 100mA per JESD78 Class II
• ESD protection exceeds JESD22 specifications
• 2000V Human Body Model
• 200V Machine Model
• 1000V Charged Device Model

• Servers
• LED displays
• Network switches
• Telecom infrastructure
• Motor drivers
• I/O expanders