TI TPS70302PWP

The TPS703xx family of devices is designed to provide a complete power management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP application with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 47 μF low ESR capacitors. These devices have fixed 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 μA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) with an overline shuts down both regulators, reducing the input current to 1 μA at junction temperature (TJ) = +25℃. The device is enabled when the EN pin with an overline is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 with an overline remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (that is, in an overload condition) of its regulated voltage, VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement an SVS (POR, or power-on reset) for the circuitry supplied by regulator 1. The TPS703xx features a RESET (SVS, POR, or power-on reset). RESET is an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up, RESET goes to a high impedance state (that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, VINI must be above the undervoltage condition. Second, the manual reset (MR with an overline) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. RESET can be used to drive power-on reset or a low-battery indicator. If RESET is not used, it can be left floating. Internal bias voltages are powered by VINI and require 2.7V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5V.

• Dual Output Voltages for Split-Supply Applications
• Independent Enable Functions (See Part Number TPS704xx for Independent Enabling of Each Output)
• Output Current Range of 1 A on Regulator 1 and 2A on Regulator 2
• Fast Transient Response
• Voltage Options: 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and Dual Adjustable Outputs
• Open Drain Power-On Reset with 120 ms Delay
• Open Drain Power Good for Regulator 1
• Ultralow 185 μA (typ) Quiescent Current
• 2 μA Input Current During Standby
• Low Noise: 78 μV_RMS Without Bypass Capacitor
• Quick Output Capacitor Discharge Feature
• Two Manual Reset Inputs
• 2% Accuracy Over Load and Temperature
• Undervoltage Lockout (UVLO) Feature
• 24-Pin PowerPAD TSSOP Package
• Thermal Shutdown Protection