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TI ADS4128IRGZTRoHS

Manufacturer
MPN
ADS4128IRGZT
LCSC Part #
C2861271
Packaging
VQFN-48-EP(7x7)
Customer #
Key Attributes
12-bit 200 MSPS ultra-low power ADC
Datasheetpdf iconTI ADS4128IRGZT
In-Stock: 1
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QtyUnit PriceTotal Amount
1+$ 44.6694$ 44.67
30+$ 42.6085$ 1278.26
Standard Packaging250/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerTI
PackagingVQFN-48-EP(7x7)
Operating Temperature-40℃~+85℃
Clock Frequency200MHz
FeaturesSoft reset;Power-on reset
InterfaceParallel port
Resolution(Bits)200MHz;12
S/N Ratio69dB
Voltage - Supply1.7V~1.9V
Number of Channels1
Integral non - linearity5LSB
Programmable GainSupport

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging250
Sales UnitPiece

Introduction

AI Translation

The ADS4128 is a 12-bit analog-to-digital converter (ADC) with a sampling rate of up to 200 MSPS. When powered by a 1.8V supply, this device uses innovative design techniques to achieve high dynamic performance while maintaining extremely low power consumption. This device is well-suited for multi-carrier, high-bandwidth communication applications. The ADS4128 features fine gain options, which can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a DC offset correction loop, which can be used to eliminate ADC offset. At lower sampling rates, the operating power consumption of the ADC will automatically decrease without any loss of performance. The ADS4128 comes in a compact, ultra-thin quad flat no-lead (VQFN)-48 package and is rated for the industrial temperature range of -40°C to 85°C.

Features

AI Translation
  • Maximum sample rate: 200MSPS
  • Ultra-low power consumption with 1.8V single supply: 230mW total power dissipation at 200MSPS
  • High dynamic performance:
    • SNR: 69dBFS at 170MHz
    • SFDR: 85dBc at 170MHz
  • Dynamic power scaling with sample rate
  • Output interface:
    • DDR with programmable swing and drive strength
    • LVDS standard swing: 350mV, low swing: 200mV, default drive strength: 100Ω termination, 2x drive strength: 50Ω termination
    • 1.8V parallel CMOS interface also supported
  • Programmable gain up to 6dB for SNR/SFDR trade-off
  • DC offset correction
  • Input clock amplitude as low as 200mVPP supported
  • Package: 7.00mm×7.00mm VQFN-48

Applications

AI Translation
  • Wireless communication infrastructure
  • Software-defined radio
  • Power amplifier linearization