TI SN74AUP1G97DRLR

The AUP family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity. The SN74AUP1G97 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to V_CC or GND. The device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. NanoStar package technology uses the die as the package. This device is fully specified for partial-power-down applications using I_0ff. The I_0ff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Available in the Texas Instruments NanoStar Package
• Low Static-Power Consumption (I_CC = 0.9 μA Max)
• Low Dynamic-Power Consumption (C_pd = 4.8 pF Typ at 3.3 V)
• Low Input Capacitance (C_I = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot < 10% of V_CC
• I_off Supports Partial-Power-Down Mode Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 5.6 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II)
• 1000-V Charged-Device Model (C101)