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TI DM3730CUSD100RoHS

Manufacturer
TI
MPN
DM3730CUSD100
LCSC Part #
C2860216
Packaging
SPBGA-423
Customer #
Key Attributes
Digital Media Processors
Datasheetpdf iconTI DM3730CUSD100

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
ManufacturerTI
PackagingSPBGA-423
CPU CoreOthers
Maximum Speed1GHz
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging90
Sales UnitPiece

Features

AI Translation
  • Compatible with OMAP 3 Architecture - ARM Microprocessor (MPU) Subsystem
    • Up to 1-GHz ARM Cortex - A8 Core Also supports 300, 600, and 800-MHz operation
    • NEON SIMD Coprocessor
    • High Performance Image, Video, Audio (IVA2.2) Accelerator Subsystem
      • Up to 800-MHz TMS320C64x+ DSP Core Also supports 260, 520, and 660-MHz operation
    • Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
    • Video Hardware Accelerators
    • POWERVR SGX Graphics Accelerator (DM3730 only)
    • Tile Based Architecture Delivering up to 20 MPoly/sec
    • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
    • Industry Standard API Support: OpenGL 1.1 and 2.0, OpenVG1.0
    • Fine Grained Task Switching, Load Balancing, and Power Management
    • Programmable High Quality Image Anti-Aliasing
    • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
    • Eight Highly Independent Functional Units
    • Six ALUs (32-/40-Bit); Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle
    • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+ Enhancements
    • Protected Mode Operation
    • Expectations Support for Error Detection and Program Redirection
    • Hardware Support for Modulo Loop Operation
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
    • 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • External Memory Interfaces:
    • SDRAM Controller (SDRC)
      • 16, 32-bit Memory Controller With 1G-Byte Total Address Space
      • Interfaces to Low-Power SDRAM
      • SDRAM Memory Scheduler (SMS) and Rotation Engine
    • General Purpose Memory Controller (GPMC)
      • 16-bit Wide Multiplexed Address/Data Bus
      • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
      • Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
      • 1.8-V I/O and 3.0-V (MMC1 only), 0.9-V to 1.2-V Adaptive Processor Core Voltage, 0.9-V to 1.1-V Adaptive Core Logic Voltage
    • Commercial, Industrial, and Extended Temperature Grades
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
    • 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
    • 5K-Byte Transmit/Receive Buffer (McBSP2)
    • SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
    • Direct Interface to I2S and PCM Device and T Buses
    • 128 Channel Transmit/Receive Mode
    • Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
    • High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
    • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
    • One HDQ/1-Wire Interface
    • Four UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Camera Image Signal Processing (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
    • Resize Images From 1/4x to 4x
    • Separate Horizontal/Vertical Control
  • System Direct Memory Access (SDMA) Controller (32 Logical Channels With Configurable Priority)
  • Comprehensive Power, Reset, and Clock Management
  • SmartReflex Technology - Dynamic Voltage and Frequency Scaling (DVFS)
  • ARM Cortex - A8 Core
    • ARMv7 Architecture
    • TrustZone
    • Thumb-2
    • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating Point SIMD
    • Jazelle RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macro Cell (ETM) Support for Non-Invasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • 32K-Byte Instruction Cache (4-Way Set-Associative)
    • 32K-Byte Data Cache (4-Way Set-Associative)
    • 256K-Byte L2 Cache
    • 32K-Byte ROM
    • 64K-Byte Shared SRAM
  • Endianess:
    • ARM Instructions - Little Endian
    • ARM Data - Configurable
    • DSP Instructions/Data - Little Endian
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
  • Test Interfaces
    • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
    • Embedded Trace Macro Interface (ETM)
    • Serial Data Transport Interface (SDTI)
  • 12 32-bit General Purpose Timers
  • 2 32-bit Watchdog Timers
  • 1 32-bit Secure Watchdog Timer
  • 1 32-bit 32-kHz Sync Timer
  • Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 45-nm CMOS Technology
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
In-Stock: 3
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QtyUnit PriceTotal Amount
1+$ 66.7042$ 66.70
10+$ 64.6683$ 646.68
Standard Packaging90/Full Reel
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