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TI CD4012BNSRRoHS

Manufacturer
TI
MPN
CD4012BNSR
LCSC Part #
C2860166
Packaging
SO-14-208mil
Customer #
Key Attributes
250nA 3V~18V SO-14-208mil Gates and Inverters RoHS
Datasheetpdf iconTI CD4012BNSR
In-Stock: 90
90 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.6057$ 0.61
10+$ 0.5919$ 5.92
30+$ 0.5827$ 17.48
100+$ 0.5735$ 57.35
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerTI
PackagingSO-14-208mil
Features-
Operating Temperature-55℃~+125℃
Logic Family4000B Series
Input Logic Level - High3.5V;7V;11V
Input Logic Level - Low1.5V;3V;4V
Output Logic Level - High4.95V;9.95V;14.95V
Quiescent Current(Iq)250nA
Voltage - Supply3V~18V
Number of Channels4;2
Current - Output High(IOH)6.8mA
Output Logic Level - Low50mV
Propagation Delay250ns@5V,50pF;120ns@10V,50pF;90ns@15V,50pF
Current - Output Low(IOL)6.8mA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMoS gates. All inputs and outputs are buffered. The CD4011B, CD4012B, and CD4023B types are supplied in 14 - lead hermetic dual - in - line ceramic packages (F3A suffix), 14 - lead dual - in - line plastic packages (E suffix), 14 - lead small - outline packages (M, MT, M96, and NSR suffixes), and 14 - lead thin shrink small - outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14 - lead thin shrink small - outline packages (PW suffix).

Features

AI Translation
  • Propagation delay time = ±50 ns (typ.) at cL = 50 pF, VDD = 10 V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics
  • Maximum input current of ±1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • 100% tested for quiescent current at 20 V
  • 5 - V, 10 - V, and 15 - V parametric ratings
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOs Devices"