LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
TI CD4093BNSR product image
  • CD4093BNSR thumbnail 1
  • CD4093BNSR thumbnail 2
  • CD4093BNSR thumbnail 3
  • Pinout
  • Footprint
Images for reference only

TI CD4093BNSRRoHS

Manufacturer
TI
MPN
CD4093BNSR
LCSC Part #
C2859897
Packaging
SO-14
Customer #
Key Attributes
Quad 2-Input NAND Schmitt Triggers
Datasheetpdf iconTI CD4093BNSR
In-Stock: 5,748
5,748 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.5059$ 0.51
10+$ 0.4278$ 4.28
30+$ 0.3725$ 11.18
100+$ 0.327$ 32.70
500+$ 0.3123$ 156.15
1,000+$ 0.3042$ 304.20
Standard Packaging2000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerTI
PackagingSO-14
Features-
Input Logic Level - High3.6V~10.8V
Input Logic Level - Low900mV~4V
Operating Temperature-55℃~+125℃
Logic Family4000B Series
Output Logic Level - High4.95V~5V
Quiescent Current(Iq)4uA
Voltage - Supply3V~18V
Current - Output High(IOH)3.4mA
Number of Channels4;2
Output Logic Level - Low50mV
Propagation Delay130ns@15V,50pF
Current - Output Low(IOL)3.4mA
Report an ErrorShow similar products (0) >

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

CD4093B consists of four Schmitt- trigger circuits. Each circuit functions as a two- input NAND gate with Schmitt- trigger action on both inputs. The gate switches at different points for positive- and negative- going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH). The CD4093B types are supplied in 14- lead hermetic dual- in- line ceramic packages (F3A suffix), 14- lead dual- in- line plastic packages (E suffix), 14- lead small- outline packages (M, MT, M96, and NSR suffixes), and 14- lead thin shrink small- outline packages (PW and PWR suffixes).

Features

AI Translation
  • Schmitt- trigger action on each input with no external components
  • Hysteresis voltage typically 0.9V at VDD = 5V and 2.3V at VDD = 10V
  • Noise immunity greater than 50%
  • No limit on input rise and fall times
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1μA at 18V over full package- temperature range, 100nA at 18V and 25℃
  • 5 - V, 10 - V, and 15 - V parametric ratings
  • Meets all requirements of JEDEC Standard No.13B, Standard Specifications for Description of V Series CMOS Devices

Applications

AI Translation
  • Wave and pulse shapers
  • High- noise- environment systems
  • Monostable multivibrators
  • Astable multivibrators
  • NAND logic