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TI SN74LVC1G374DCKR product image
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TI SN74LVC1G374DCKRRoHS

Manufacturer
MPN
SN74LVC1G374DCKR
LCSC Part #
C2859827
Packaging
SC-70-6
Customer #
Key Attributes
Single D-Type Flip-Flop With 3-State Output
Datasheetpdf iconTI SN74LVC1G374DCKR

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingSC-70-6
Operating Temperature-40℃~+125℃
Voltage - Supply1.65V~5.5V
Number of Bits per Element1
Series74LVC Series
Output TypeTri-State
Number of Elements1
Current - Output High(IOH)32mA
Current - Output Low(IOL)32mA
Setup Time1.5ns
Quiescent Current10uA
Hold Time1.5ns
Propagation Delay4ns@5V,50pF
Trigger TypeRising Edge

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

This single D-type latch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE(overline)) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flipflop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

AI Translation
  • Available in the Texas Instruments NanoStar and NanoFree Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 4 ns at 3.3 V
  • Low Power Consumption, 10 μA Max ICC
  • ±24 mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)

Applications

AI Translation
  • buffer registers
  • input/output (I/O) ports
  • bidirectional bus drivers
  • working registers
In-Stock: 12,060
12,060 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.1634$ 0.82
50+$ 0.1283$ 6.42
150+$ 0.1111$ 16.67
500+$ 0.0958$ 47.90
3,000+$ 0.0916$ 274.80
6,000+$ 0.0891$ 534.60
Standard Packaging3000/Full Reel
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