TI SN74LVC1G374DCKR
| Manufacturer | |
| MPN | SN74LVC1G374DCKR |
| LCSC Part # | C2859827 |
| Packaging | SC-70-6 |
| Customer # | |
| Key Attributes | Single D-Type Flip-Flop With 3-State Output |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SC-70-6 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Bits per Element | 1 | |
| Series | 74LVC Series | |
| Output Type | Tri-State | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA | |
| Setup Time | 1.5ns | |
| Quiescent Current | 10uA | |
| Hold Time | 1.5ns | |
| Propagation Delay | 4ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This single D-type latch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE(overline)) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flipflop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoStar and NanoFree Packages
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Provides Down Translation to VCC
- Max tpd of 4 ns at 3.3 V
- Low Power Consumption, 10 μA Max ICC
- ±24 mA Output Drive at 3.3 V
- Ioff Supports Live Insertion, Partial-Power Down Mode, and Back Drive Protection
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
Applications
- buffer registers
- input/output (I/O) ports
- bidirectional bus drivers
- working registers
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1634 | $ 0.82 |
| 50+ | $ 0.1283 | $ 6.42 |
| 150+ | $ 0.1111 | $ 16.67 |
| 500+ | $ 0.0958 | $ 47.90 |
| 3,000+ | $ 0.0916 | $ 274.80 |
| 6,000+ | $ 0.0891 | $ 534.60 |
Standard Packaging3000/Full Reel | ||
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



