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ST M34E02-FDW6TPRoHS

Manufacturer
MPN
M34E02-FDW6TP
LCSC Part #
C283450
Packaging
TSSOP-8
Customer #
Key Attributes
2-Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1, DDR2 and DDR3) DRAM modules
Datasheetpdf iconST M34E02-FDW6TP
In-Stock: 15
15 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.2212$ 0.22
10+$ 0.1715$ 1.72
30+$ 0.1502$ 4.51
100+$ 0.1236$ 12.36
500+$ 0.1117$ 55.85
1,000+$ 0.1046$ 104.60
Standard Packaging4000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerST
PackagingTSSOP-8
Memory Size2Kbit
Voltage - Supply1.7V~5.5V
Operating temperature-40℃~+85℃
Clock Frequency400kHz
FeaturesHardware write protection function;Software write protection function;Built-in power-on reset (POR);Noise suppression function
Data Retention - TDR (Year)40 Years
Write Cycle Time(tWC)5ms
Write Cycle Endurance1,000,000 cycles
InterfaceI2C

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging4000
Sales UnitPiece

Introduction

AI Translation

The M34E02-F is a 2-Kbit |²C -compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 256x8 bits. The M34E02-F can be accessed with a supply voltage from 1.7 V to 5.5 V and operates with a clock frequency of 400 kHz (or less), over an ambient temperature range of -40 ℃ / +85 ℃. The M34E02-F is able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD). All the information concerning the DDR1, DDR2 or DDR3 configuration of the DRAM module (such as its access speed, size and organization) can be kept write-protected in the first half of the memory. The first half of the memory area can be write-protected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. In addition, the devices allow the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC). These |²C -compatible electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits. |²C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the |²C bus definition to access the memory area and a second device type identifier code (0110) to define the protection. These codes are used together with the voltage level applied on the three chip enable inputs (E2, E1, E0). The devices behave as a slave device in the |²C protocol, with all memory operations synch

Features

AI Translation
  • 2-Kbit EEPROM for DDR1, DDR2 and DDR3 serial presence detect
  • Backward compatible with the M34C02
  • Permanent and reversible software data protection for lower 128 bytes
  • 100 kHz and 400 kHz I²C bus serial interface
  • Single supply voltage: 1.7 V to 5.5 V
  • Byte and Page Write (up to 16 bytes)
  • Self-timed write cycle
  • Noise filtering – Schmitt trigger on bus inputs
  • Noise filter on bus inputs
  • Enhanced ESD/latch-up protection
  • More than 1 million erase/write cycles
  • More than 40 years’ data retention
  • ECOPACK (RoHS compliant) packages
  • Packages: ECOPACK2 (RoHS-compliant and Halogen-free)