GOSEMICON GBP65200GPMAR

The GBP65200G is a 650V GaN Power Stage, optimized for high frequency, soft-switching topologies. The monolithic integration of GaN, driver and logic create an easy-to-use high-performance powertrain building block, enabling designers to create the fastest, smallest, most efficient integrated powertrain. Down to -5V input capability enhances the input noise immunity. Very low quiescent current reduces the stand by power loss in the power converter. The device adopts non-overlap driver design to avoid the shoot-through of output stage. The GBP65200G is a 650V GaN Power Stage, integrated high-speed driver and a 150 mΩ GaN HEMT, which is optimized for high frequency, soft-switching topologies. Up to 1MHz switching frequency allows designers to develop higher power density power supply. The GBP65200G supports wide PWM input hysteresis which is compatible for TTL low voltage logic. TTL logic input simplifies the PWM input circuit design without any extra buffer or level shift circuit. Meanwhile, the wide hysteresis increases the noise immunity. The GBP65200G has very low quiescent current that reduces the standby power loss in the power converter. A 6.2V LDO is integrated in the gate driver, the LDO supplies the power to the gate of HEMT GaN directly, which simplifies the off chip components and minimize the PCB board in the layout. The GBP65200G internal driver provides minimum propagation delay 15ns from input to output. The ability to handle -5V DC input increases the driver input stage noise immunity, and the rail-to-rail driver improves the GBP65200G output stage robustness during the switching load fast transition. The GBP65200G supply voltage is ranging between 7V to 20V. For best circuit performance, two VDD bypass capacitors in parallel are recommended to prevent noise problems on supply VDD. A 0.1-μF surface mount ceramic capacitor must be located as close as possible to the VDD to GND pins. In addition, a bigvalue capacitor (exp. 1μF or 10uF) with relatively low ESR must be connected in parallel, in order to avoid unexpected VDD supply glitch. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in the application. The PWM input is compatible to TTL logic, which make the device easy-to-use by PWM control signals. The wide input hysteresis, with typically 3.1V high threshold and 1.1V low threshold, offers enhanced noise immunity compared to traditional TTL logic implementation. GBP65200G also features tight control of the input threshold voltage that ensures stable operation across temperature. The low input capacitance on the input pins increases switching speed and reduces the propagation delay. The GBP65200G implements the Under Voltage Lock Out (UVLO) with rising threshold of typically 5 V along with 500mV typical hysteresis. The UVLO holds the output low regardless of the input status when VDD is rising but the level is below the UVLO threshold. The hysteresis prevents output bouncing for avoiding the noise impact on the power supply. During power up, the driver output remains low until the VDD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with VDD till steady state VDD reached. The GBP65200G holds the driver low when VDD is below Under Voltage Lock Out threshold (VDD_UVLO).

• Monolithically-Integrated gate driver
• 7V - 20V Wide Supply Voltage Range
• -5V - 20V Wide Logic Input Voltage Capability
• TTL Input-Logic Threshold
• 650V GaN HEMT with Low 150 mΩ On Resistance
• Zero reverse recovery charge
• Up to 1 MHz operation
• Low Quiescent Current: 120uA
• Output Low When Input Floating
• Available in PDFN 5x6 mm Package

• AC-DC, DC-DC Buck, boost, half bridge, full bridge
• Active Clamp Flyback, LLC resonant
• Mobile fast-chargers, adapters
• Notebook adaptors
• LED lighting, solar micro-inverters
• TV / monitor, wireless power
• Server, telecom & networking SMPS
• BOOST
• Half Bridge