Nexperia 74LV14D,118

The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V(T+) and the negative voltage V(T-) is defined as the input hysteresis voltage VH.

• Wide supply voltage range from 1.0 V to 5.5 V
• CMOS low power dissipation
• Optimized for low voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between V(CC)=2.7 V and V(CC)=3.6 V
• Typical output ground bounce <0.8 V at V(CC)=3.3 V and T(amb)=25 °C
• Typical HIGH-level output voltage (V(0H)) undershoot: >2 V at V(CC)=3.3 V and T(amb)=25 °C
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
  • JESD8-7 (1.65 V to 1.95 V)
  • JESD8-5 (2.3 V to 2.7 V)
  • JESD8C (2.7 V to 3.6 V)
  • JESD36 (4.5 V to 5.5 V)
• ESD protection:
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wave and pulse shapers for highly noisy environments
• Astable multivibrators
• Monostable multivibrators