AMD/XILINX XC3S250E-4VQG100I

The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards • 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling • 622+ Mb/s data transfer rate per I/O True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O Enhanced Double Data Rate (DDR) support DDR SDRAM support up to 333 Mb/s

Abundant, flexible logic resources

Densities up to 33,192 logic cells, including optional shift register or distributed RAM support Efficient wide multiplexers, wide logic Fast look-ahead carry logic • Enhanced 18x18 multipliers with optional pipeline IEEE 1149.1/1532 JTAG programming/debug port

Hierarchical SelectRAM™ memory architecture

Up to 648 Kbits of fast block RAM Up to 231 Kbits of efficient distributed RAM

Clock skew elimination (delay locked loop) Frequency synthesis, multiplication, division High-resolution phase shifting Wide frequency range (5 MHz to over 300 MHz)

Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing

Configuration interface to industry-standard PROMs • Low-cost, space-saving SPI serial Flash PROM • x8 or x8/x16 parallel NOR Flash PROM Low-cost Xilinx® Platform Flash with JTAG

• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 376 I/O pins or 156 differential signal pairs

• broadband access
• home networking
• display/projection
• digital television equipment