TI SN74LS74ANSR

These devices contain two independent D-type positive-edge-triggered flip-flops. A low ievel at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock puise. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock puise. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.