TI SN74AHCT273NSR
| Manufacturer | |
| MPN | SN74AHCT273NSR |
| LCSC Part # | C2677697 |
| Packaging | SO-20-208mil |
| Customer # | |
| Key Attributes | 4.5V~5.5V 9.2ns@5V,50pF SO-20-208mil Flip Flops RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SO-20-208mil | |
| Voltage - Supply | 4.5V~5.5V | |
| Series | 74AHCT Series | |
| Output Type | - | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Quiescent Current | 4uA | |
| Propagation Delay | 9.2ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
These devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR(overline)) input. These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR(overline)) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D in
Applications
- Buffers and Storage Registers
- Shift Registers
- Pattern Generators
- Servers
- PCs and Notebooks
- Network Switches
- Memory Systems Databases
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.5818 | $ 0.58 |
| 10+ | $ 0.5688 | $ 5.69 |
| 30+ | $ 0.5607 | $ 16.82 |
| 100+ | $ 0.551 | $ 55.10 |
Standard Packaging2000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SO-20-208mil | |
| Voltage - Supply | 4.5V~5.5V | |
| Series | 74AHCT Series | |
| Output Type | - | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Quiescent Current | 4uA | |
| Propagation Delay | 9.2ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
These devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR(overline)) input. These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR(overline)) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D in
Applications
- Buffers and Storage Registers
- Shift Registers
- Pattern Generators
- Servers
- PCs and Notebooks
- Network Switches
- Memory Systems Databases
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



