TI UCC27524ADGNR

The UCC27524A device is a dual-channel, high-speed, low-side gate driver capable of effectively driving MOSFET and IGBT power switches. To enhance robustness and durability, the UCC27524A adds the ability to directly handle –5V voltages on the input pins.

The UCC27524A is a dual non-inverting driver. Utilizing a design that greatly reduces shoot-through current internally, the UCC27524A can deliver high peak current pulses of up to 5A source and 5A sink to capacitive loads. The device also features rail-to-rail drive capability and an exceptionally low propagation delay with a typical value of 13ns. In addition, the driver features matched internal propagation delays between the two channels, making it well-suited for applications with stringent dual gate drive timing requirements, such as synchronous rectifiers. This also allows the two channels to be paralleled to effectively increase current drive capability, or to drive two switches connected in parallel using a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. The wide hysteresis between high and low thresholds provides excellent noise immunity.

For safety considerations, internal pull-up and pull-down resistors on the UCC27524A input pins ensure the outputs are held low when the input pins are left floating. The UCC27524A features enable pins (ENA and ENB) for better control over driver operation. These pins are internally pulled up to VDD for active-high logic and can be left open for standard operation.

The UCC27524A series devices are available in SOIC-8 (D), VSSOP-8, and SOIC-8 with exposed pad (DGN) packages.

• Industry-standard pinout
• Dual independent gate drive channels
• 5A peak source and sink drive current
• Independent enable function per output
• TTL and CMOS compatible logic thresholds independent of supply voltage
• Hysteretic logic thresholds for high noise immunity
• Capable of handling negative voltage (-5V) at inputs
• Input and enable pin voltage levels independent of VDD bias supply voltage
• 4.5V to 18V single-supply range
• Output held low during VDD UVLO (ensures glitch-free operation during power-up and power-down)
• Fast propagation delay (13ns typical)
• Fast rise and fall times (7ns and 6ns typical)
• Delay matching between two channels: 1ns typical
• Two outputs parallelable for higher drive current
• Output held low when input is floating
• SOIC-8, HVSSOP-8 PowerPAD package options
• Operating temperature range: -40°C to 140°C

• Switch-mode power supplies
• DC-to-DC converters
• Motor control, solar
• Gate driving for emerging wide-bandgap power devices such as GaN