TI SN74AUP2G125YZPR
| Manufacturer | |
| MPN | SN74AUP2G125YZPR |
| LCSC Part # | C2676075 |
| Packaging | DSBGA-8(1.9x1.9) |
| Customer # | |
| Key Attributes | 0.8V~3.6V 1 2 2.3ns@3.3V,5pF 900nA DSBGA-8(1.9x1.9) Buffers, Drivers, Receivers, Transceivers RoHS |
| Datasheet |  TI SN74AUP2G125YZPR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | DSBGA-8(1.9x1.9) | |
| Input type | - | |
| Voltage - Supply | 0.8V~3.6V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 4mA | |
| Series | 74AUP | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 4mA | |
| Number of Bits per Element | 1 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 2.3ns@3.3V,5pF | |
| Quiescent Current | 900nA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AUP family ensures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V V_CC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE(overline)) input is high. This device has the input-disable feature, which allows floating input signals. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoStar Package
- Low Static-Power Consumption (I_CC = 0.9 μA Max)
- Low Dynamic-Power Consumption (C_pd = 4 pF Typ at 3.3 V)
- Low Input Capacitance (C_I = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot < 10% of V_CC
- Input-Disable Feature Allows Floating Input Conditions
- I_off Supports Partial-Power-Down Mode Operation
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
- Wide Operating V_CC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- t_pd = 5.4 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.4362 | $ 0.44 |
| 10+ | $ 0.425 | $ 4.25 |
| 30+ | $ 0.4169 | $ 12.51 |
| 100+ | $ 0.4105 | $ 41.05 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | DSBGA-8(1.9x1.9) | |
| Input type | - | |
| Voltage - Supply | 0.8V~3.6V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 4mA | |
| Series | 74AUP | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 4mA | |
| Number of Bits per Element | 1 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 2.3ns@3.3V,5pF | |
| Quiescent Current | 900nA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AUP family ensures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V V_CC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE(overline)) input is high. This device has the input-disable feature, which allows floating input signals. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoStar Package
- Low Static-Power Consumption (I_CC = 0.9 μA Max)
- Low Dynamic-Power Consumption (C_pd = 4 pF Typ at 3.3 V)
- Low Input Capacitance (C_I = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot < 10% of V_CC
- Input-Disable Feature Allows Floating Input Conditions
- I_off Supports Partial-Power-Down Mode Operation
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
- Wide Operating V_CC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- t_pd = 5.4 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |