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TI SN74AUP1G126YZPRRoHS

Manufacturer
TI
MPN
SN74AUP1G126YZPR
LCSC Part #
C2676022
Packaging
DSBGA-5(0.9x1.4)
Customer #
Key Attributes
Low-Power Single Bus Buffer Gate With Tri-State Output
Datasheetpdf iconTI SN74AUP1G126YZPR
In-Stock: 294
294 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.5058$ 0.51
10+$ 0.4021$ 4.02
30+$ 0.3574$ 10.72
100+$ 0.3016$ 30.16
500+$ 0.2761$ 138.05
1,000+$ 0.2617$ 261.70
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerTI
PackagingDSBGA-5(0.9x1.4)
Input typeSchmitt trigger
Voltage - Supply0.8V~3.6V
Output TypeTri-State
Current - Output High(IOH)4mA
Series74AUP
Operating Temperature-40℃~+85℃
Current - Output Low(IOL)4mA
Number of Bits per Element1
Channel TypeUnidirectional
FeaturesPower-off isolation;Output enable
Number of Elements1
Propagation Delay4.6ns@3.3V,5pF
Quiescent Current900nA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The LowestPower Family and Excellent Signal Integrity ).

This bus buffer gate is a single line driver with a 3- state output. The output is disabled when the outputenable (OE) input is low. This device has the inputdisable feature, which allows floating input signals.

To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Features

AI Translation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22− 2000-V Human-Body Model (A114-B, Class II) 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption (IC C = 0.9 μA Maximum)
  • Low Dynamic-Power Consumption (Δ(Cp d = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

Applications

AI Translation
  • Audio Dock: Portable
  • BluRay™Players and Home Theaters
  • Personal Digital Assistant (PDA)
  • Power: Telecom/Server AC/DC Supply: Single
  • Controller: Analog and Digital
  • Solid-State Drive (SSD): Client and Enterprise
  • TV: LCD/Digital and High-Definition (HDTV)
  • Tablet: Enterprise
  • Wireless Headsets, Keyboards, and Mice