TI SN74AUC2G240DCTR
| Manufacturer | |
| MPN | SN74AUC2G240DCTR |
| LCSC Part # | C2675872 |
| Packaging | SSOP-8 |
| Customer # | |
| Key Attributes | DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SSOP-8 | |
| Input type | - | |
| Voltage - Supply | 0.8V~2.7V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 9mA | |
| Series | 74AUC | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 9mA | |
| Number of Bits per Element | 1 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 1.8ns@1.8V,15pF | |
| Quiescent Current | 10uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual buffer/driver is operational at 0.8 V to 2.7 VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE(overline)) inputs. When OE(overline) is low, the device passes data from the A input to the Y output. When OE(overline) is high, the outputs are in the high-impedance state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoFree Package
- Optimized for 1.8-V Operation and Is 3.6-V I/O
- Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max tp d of 1.8 ns at 1.8 V
- Low Power Consumption, 10 μA at 1.8 V
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.8041 | $ 0.80 |
| 10+ | $ 0.785 | $ 7.85 |
| 30+ | $ 0.7738 | $ 23.21 |
| 100+ | $ 0.7611 | $ 76.11 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SSOP-8 | |
| Input type | - | |
| Voltage - Supply | 0.8V~2.7V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 9mA | |
| Series | 74AUC | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 9mA | |
| Number of Bits per Element | 1 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 2 | |
| Propagation Delay | 1.8ns@1.8V,15pF | |
| Quiescent Current | 10uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual buffer/driver is operational at 0.8 V to 2.7 VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE(overline)) inputs. When OE(overline) is low, the device passes data from the A input to the Y output. When OE(overline) is high, the outputs are in the high-impedance state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoFree Package
- Optimized for 1.8-V Operation and Is 3.6-V I/O
- Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max tp d of 1.8 ns at 1.8 V
- Low Power Consumption, 10 μA at 1.8 V
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

