TI SN74LV4040AMPWREP

The SN74LV4040A device is a 12 bit asynchronous binary counter with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

• Controlled Baseline – One Assembly – Test Site – One Fabrication Site
• Extended Temperature Performance of -55℃ to 125℃
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• 2-V to 5.5V CC Operation
• Typical VoLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25℃
• Typical V0HV (Output v0H Undershoot) > 2.3V at VCC = 3.3V, TA = 25℃
• Support Mixed-Mode Voltage Operation on All Ports
• High On-Off Output-Voltage Ratio
• Low Crosstalk Between Switches
• Individual Switch Controls
• Extremely Low Input Current
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

• time-delay circuits
• counter controls
• frequency-dividing circuits