TI SN74LV4040ADR

The 'LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits. These devices are fully specified for partial-power-down applications using the Ioff condition. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

• 2-V to 5.5-V Vcc Operation
• Support Mixed-Mode Voltage Operation on All Ports
• High On-Off Output-Voltage Ratio
• Low Crosstalk Between Switches
• Individual Switch Controls
• Extremely Low Input Current Ioff
• Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD78, Class II
• ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

• time-delay circuits
• counter controls
• frequency-dividing circuits