TI SN74HC138DRE4

The SNx4HC138 device is designed for high-performance memory decoding or data routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the impact of system decoding. When used with high-speed memories utilizing high-speed enable circuitry, the combined delay time of the decoder and the enable time of the memory are typically less than the typical access time of the memory. This means the effective system delay introduced by the decoder is negligible.

The SNx4HC138 device is a 3-to-8 line decoder and demultiplexer. Three input pins A, B, and C select which output is active. The selected output is pulled low while all remaining outputs are held high. Binary select inputs at three enable inputs conditionally select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters during expansion. A 24-line decoder can be implemented without external inverters, while a 32-line decoder requires only one inverter. The enable inputs can be used as data inputs in demultiplexer applications.

• Optimized for high-speed memory decoders and data transmission systems
• Wide operating voltage range (2V to 6V)
• Outputs capable of driving up to 10 LSTTL loads
• Low power consumption, ICC max = 80μA
• t(pd) typical = 15ns
• ±4mA output drive (at 5V)
• Low input current, max 1μA
• Active-low outputs (selected output goes low)
• Three enable inputs for simplified cascading or data reception

• LED displays
• Servers
• Large home appliances
• Power infrastructure
• Building automation
• Factory automation