TI CD74HCT138M96

The CDx4HC(T)138 and '238 are 3-line to 8-line decoders with one standard output strobe (G₂) and two active-low output strobes (G₁ and G₀). When the outputs are controlled by any strobe input, all outputs are forced to the high state. When the strobe inputs do not disable the outputs, only the selected output is low while all other outputs remain high. The CDx4HC(T)238 is a 3-line to 8-line decoder with one standard output strobe (G₂) and two active-low output strobes (G₁ and G₀(overline)). When the outputs are controlled by any strobe input, all outputs are forced to the low state. When the strobe inputs do not disable the outputs, only the selected output is high while all other outputs remain low. The CDx4HC(T)138 and '238 are high-speed silicon-gate CMOS decoders, ideally suited for memory address decoding or data routing applications. They incorporate a single 3:8 decoder. The CDx4HC(T)138 and '238 have three address select inputs (A₂, A₁, and A₀). The circuit operates as a standard one-of-eight decoder. Three strobe inputs (G₂, G₁(overline), and G₀(overline)) are provided to simplify cascading and facilitate demultiplexing. For the '138 function, when any strobe input is asserted, all outputs are forced to the high state. For the '238 function, when any strobe input is asserted, all outputs are forced to the low state. The demultiplexing function is achieved by first using the select inputs to choose the desired output, then using one of the strobe inputs as the data input. The CDx4HC(T)138 outputs are normally low when selected. The CDx4HC(T)238 outputs are normally high when selected.

• Selects one-of-eight data outputs
• Active LOW for '138, active HIGH for '238
• I/O port or memory selector
• Three enable inputs to simplify cascaded fan-out (over temperature range)
• Wide operating temperature range: -55℃ to 125℃
• Balanced propagation delays and transition times
• Significantly reduced power consumption compared to LSTTL logic ICs
• HC type: operating voltage 2 V to 6 V
• HC type: high noise immunity: N₁L = 30%, NIH = 30% of VCC when VCC = 5 V
• HCT type: 4.5 V to 5.5 V operating voltage
• HCT type: direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
• HCT type: CMOS input compatibility, Il ≤ 1μA at VOL, VOH

• Memory address decoding
• Data routing