RENESAS 89HPES4T4G2ZCALGI8

Utilizing standard PCI Express interconnect the PES4T4G2 provides the most efficient high-performance I/O connectivity device for applications requiring high throughput, low latency and simple board layout. It provides PCI Express connectivity across 4 lanes and 4 ports. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 2.0. The PES4T4G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES4T4G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity.

• Four Gen2 PCI Express lanes supporting 5 Gbps and 2.5 Gbps operations
• Four switch ports
• One x1 upstream port
• Three x1 downstream ports
• Low latency cut-through switch architecture
• Support for Max Payload Size up to 2Kbytes
• Supports one virtual channel and eight traffic classes
• PCI Express Base Specification Revision 2.0 compliant
• Automatic lane reversal on all ports
• Automatic polarity inversion
• Ability to load device configuration from serial EEPROM
• PCI compatible INTx emulation
• Bus locking
• Requires no external components
• Incorporates on-chip internal memory for packet buffering and queueing
• Integrates four 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)
• Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC)
• Supports ECRC and Advanced Error Reporting
• All internal data and control RAMs are SECDED ECC protected
• Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
• Compatible with Hot-Plug I/O expanders used on PC motherboards
• Supports Hot-Swap
• Utilizes advanced low-power design techniques to achieve low typical power consumption
• Support PCI Power Management Interface specification (PCI PM 2.0)
• Supports device power management states: D0, D3hot and D3cold
• Support for PCI Express Active State Power Management (ASPM) link state
• Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3
• Supports PCI Express Power Budgeting Capability
• Configurable SerDes power consumption
• Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode
• Supports numerous SerDes Transmit Voltage Margin settings
• Unused SerDes are disabled
• Built in Pseudo-Random Bit Stream (PRBS) generator
• Numerous SerDes test modes
• Ability to read and write any internal register via the SMBus
• Ability to bypass link training and force any link into any mode
• Provides statistics and performance counters
• Each pin may be individually configured as an input or output
• Each pin may be individually configured as an interrupt input
• Some pins have selectable alternate functions