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RENESAS 89HPEB383ZBEMG8 product image
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RENESAS 89HPEB383ZBEMG8RoHS

Manufacturer
MPN
89HPEB383ZBEMG8
LCSC Part #
C2674256
Packaging
TQFP-128(14x14)
Customer #
Key Attributes
PEB383 x1 PCI Express to 32b/66MHz PCI Bridge
Datasheetpdf iconRENESAS 89HPEB383ZBEMG8
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QtyUnit Price(Reference Only)Total Amount
1+$ 17.9587$ 17.96
200+$ 6.9496$ 1389.92
750+$ 6.7058$ 5029.35
1,500+$ 6.5855$ 9878.25
Standard Packaging750/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Specialized
ManufacturerRENESAS
PackagingTQFP-128(14x14)
FeaturesPower-up/reset configuration

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging750
Sales UnitPiece

Introduction

AI Translation

The PEB383 is a bridge that interfaces x1 PCI Express to 32b/66MHz PCI. This bridge is specified for consumer applications providing a solution with ultra low power and highest performance in a small package footprint. The PEB383 as a transparent bridge is plug and play that requires no special configuration and will initialize under standard BIOS enumeration.

Features

AI Translation
  • Compliant with:
    • PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0)
    • PCI-to-PCI Bridge Specification (Revision 1.2)
  • Supports two modes of addressing:
    • Transparent: For efficient, flow-through configurations
    • Non-transparent: For address remapping of the PCIe and the PCI domains
  • Packaging designed for PCB escape routing in 4-layers
    • 14x14mm, 128 pin QFP
    • 10x10mm, 132 pin QFN
  • Support for Masquerade mode (can overwrite vendor and device ID from EEPROM)
  • Support for Subsystem ID (SSID) and Subsystem Vendor ID (SSVID)
  • JTAG IEEE 1149.1, 1149.6
  • Lowest active and standby power
  • Compliant with PCI Bus Power Management Interface Specification (Revision 1.2)
  • Support for D0, D3 hot, D3 cold power management states
  • ASPM L0s link state power management
  • ASPM L1
  • Standby power: 130mW
  • Common PCH (Platform Controller Hub) Supply Voltages
  • Supply Tolerance +/- 10%
  • High throughput and low latency
  • 5 times the standard read performance using Short-Term Caching
  • Compliant with PCI Express Base Specification (Revision 1.1)
  • 128-byte maximum payload
  • Advanced error reporting (AER) capability
  • End-to-end CRC (ECRC) check and generation
  • Up to four outstanding memory reads
  • 512-byte read completion buffer
  • Legacy interrupt signaling
  • Compliant with PCI Local Bus Specification (Revision 3.0)
  • 5V tolerant IO with VIO pins for added reliability and device protection
  • Up to 66-MHz PCI bus operation
  • Up to four outstanding read requests
  • 1-KB read completion buffer
  • Support for four external PCI bus masters through an integrated arbiter
  • 5V tolerant IO with VIO pins for added reliability and device protection
  • Subtractive decode support in order to forward legacy cycles through the bridge

Applications

AI Translation
  • Motherboards
  • Digital video recorders (video surveillance)
  • Set-top box
  • Express cards for mobile devices
  • PC adapter cards
  • Multifunction printer
  • Communication line cards
  • NICs